A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technolog...
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Autor*in:	Dehghani, Abbas [verfasserIn] Jamshidi, Kamal [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2015

Schlagwörter:	Network on chip Wireless interconnections Permanent faults Fault-tolerance Multicore systems

Übergeordnetes Werk:	Enthalten in: The journal of supercomputing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1987, 71(2015), 8 vom: 24. Apr., Seite 3116-3148
Übergeordnetes Werk:	volume:71 ; year:2015 ; number:8 ; day:24 ; month:04 ; pages:3116-3148

Links:	Volltext

DOI / URN:	10.1007/s11227-015-1430-z

Katalog-ID:	SPR017922259

Internformat


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520			\|a Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns.
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700	1		\|a Jamshidi, Kamal \|e verfasserin \|4 aut
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publishDate	2015
allfields	10.1007/s11227-015-1430-z doi (DE-627)SPR017922259 (SPR)s11227-015-1430-z-e DE-627 ger DE-627 rakwb eng 004 620 ASE 54.20 bkl Dehghani, Abbas verfasserin aut A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns. Network on chip (dpeaa)DE-He213 Wireless interconnections (dpeaa)DE-He213 Permanent faults (dpeaa)DE-He213 Fault-tolerance (dpeaa)DE-He213 Multicore systems (dpeaa)DE-He213 Jamshidi, Kamal verfasserin aut Enthalten in The journal of supercomputing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1987 71(2015), 8 vom: 24. Apr., Seite 3116-3148 (DE-627)271350202 (DE-600)1479917-0 1573-0484 nnns volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148 https://dx.doi.org/10.1007/s11227-015-1430-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 54.20 ASE AR 71 2015 8 24 04 3116-3148
spelling	10.1007/s11227-015-1430-z doi (DE-627)SPR017922259 (SPR)s11227-015-1430-z-e DE-627 ger DE-627 rakwb eng 004 620 ASE 54.20 bkl Dehghani, Abbas verfasserin aut A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns. Network on chip (dpeaa)DE-He213 Wireless interconnections (dpeaa)DE-He213 Permanent faults (dpeaa)DE-He213 Fault-tolerance (dpeaa)DE-He213 Multicore systems (dpeaa)DE-He213 Jamshidi, Kamal verfasserin aut Enthalten in The journal of supercomputing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1987 71(2015), 8 vom: 24. Apr., Seite 3116-3148 (DE-627)271350202 (DE-600)1479917-0 1573-0484 nnns volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148 https://dx.doi.org/10.1007/s11227-015-1430-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 54.20 ASE AR 71 2015 8 24 04 3116-3148
allfields_unstemmed	10.1007/s11227-015-1430-z doi (DE-627)SPR017922259 (SPR)s11227-015-1430-z-e DE-627 ger DE-627 rakwb eng 004 620 ASE 54.20 bkl Dehghani, Abbas verfasserin aut A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns. Network on chip (dpeaa)DE-He213 Wireless interconnections (dpeaa)DE-He213 Permanent faults (dpeaa)DE-He213 Fault-tolerance (dpeaa)DE-He213 Multicore systems (dpeaa)DE-He213 Jamshidi, Kamal verfasserin aut Enthalten in The journal of supercomputing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1987 71(2015), 8 vom: 24. Apr., Seite 3116-3148 (DE-627)271350202 (DE-600)1479917-0 1573-0484 nnns volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148 https://dx.doi.org/10.1007/s11227-015-1430-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 54.20 ASE AR 71 2015 8 24 04 3116-3148
allfieldsGer	10.1007/s11227-015-1430-z doi (DE-627)SPR017922259 (SPR)s11227-015-1430-z-e DE-627 ger DE-627 rakwb eng 004 620 ASE 54.20 bkl Dehghani, Abbas verfasserin aut A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns. Network on chip (dpeaa)DE-He213 Wireless interconnections (dpeaa)DE-He213 Permanent faults (dpeaa)DE-He213 Fault-tolerance (dpeaa)DE-He213 Multicore systems (dpeaa)DE-He213 Jamshidi, Kamal verfasserin aut Enthalten in The journal of supercomputing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1987 71(2015), 8 vom: 24. Apr., Seite 3116-3148 (DE-627)271350202 (DE-600)1479917-0 1573-0484 nnns volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148 https://dx.doi.org/10.1007/s11227-015-1430-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 54.20 ASE AR 71 2015 8 24 04 3116-3148
allfieldsSound	10.1007/s11227-015-1430-z doi (DE-627)SPR017922259 (SPR)s11227-015-1430-z-e DE-627 ger DE-627 rakwb eng 004 620 ASE 54.20 bkl Dehghani, Abbas verfasserin aut A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms 2015 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns. Network on chip (dpeaa)DE-He213 Wireless interconnections (dpeaa)DE-He213 Permanent faults (dpeaa)DE-He213 Fault-tolerance (dpeaa)DE-He213 Multicore systems (dpeaa)DE-He213 Jamshidi, Kamal verfasserin aut Enthalten in The journal of supercomputing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1987 71(2015), 8 vom: 24. Apr., Seite 3116-3148 (DE-627)271350202 (DE-600)1479917-0 1573-0484 nnns volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148 https://dx.doi.org/10.1007/s11227-015-1430-z lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_206 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 54.20 ASE AR 71 2015 8 24 04 3116-3148
language	English
source	Enthalten in The journal of supercomputing 71(2015), 8 vom: 24. Apr., Seite 3116-3148 volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148
sourceStr	Enthalten in The journal of supercomputing 71(2015), 8 vom: 24. Apr., Seite 3116-3148 volume:71 year:2015 number:8 day:24 month:04 pages:3116-3148
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Network on chip Wireless interconnections Permanent faults Fault-tolerance Multicore systems
dewey-raw	004
isfreeaccess_bool	false
container_title	The journal of supercomputing
authorswithroles_txt_mv	Dehghani, Abbas @@aut@@ Jamshidi, Kamal @@aut@@
publishDateDaySort_date	2015-04-24T00:00:00Z
hierarchy_top_id	271350202
dewey-sort	14
id	SPR017922259
language_de	englisch
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author	Dehghani, Abbas
spellingShingle	Dehghani, Abbas ddc 004 bkl 54.20 misc Network on chip misc Wireless interconnections misc Permanent faults misc Fault-tolerance misc Multicore systems A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms
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topic_title	004 620 ASE 54.20 bkl A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms Network on chip (dpeaa)DE-He213 Wireless interconnections (dpeaa)DE-He213 Permanent faults (dpeaa)DE-He213 Fault-tolerance (dpeaa)DE-He213 Multicore systems (dpeaa)DE-He213
topic	ddc 004 bkl 54.20 misc Network on chip misc Wireless interconnections misc Permanent faults misc Fault-tolerance misc Multicore systems
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title	A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms
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title_full	A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms
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title_sort	fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms
title_auth	A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms
abstract	Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns.
abstractGer	Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns.
abstract_unstemmed	Abstract Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previous works on WNoC systems. In this article, a fault-tolerant hierarchical hybrid WNoC architecture is proposed. First, an innovative strategy is proposed for solving the problem of fault-tolerant wireless routers placement in standard mesh networks inspired by node-disjoint communication structures. Next, efficient fault-tolerant communication protocols are presented for applying this structure. The experimental results demonstrate the robustness of this proposed architecture in the presence of various fault regions under different traffic patterns.
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container_issue	8
title_short	A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms
url	https://dx.doi.org/10.1007/s11227-015-1430-z
remote_bool	true
author2	Jamshidi, Kamal
author2Str	Jamshidi, Kamal
ppnlink	271350202
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hochschulschrift_bool	false
doi_str	10.1007/s11227-015-1430-z
up_date	2024-07-03T16:06:12.735Z
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A fault-tolerant hierarchical hybrid mesh-based wireless network-on-chip architecture for multicore platforms

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