Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms
Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systoli...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Roychowdhury, V. P. [verfasserIn] Kailath, T. [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
1989 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 1(1989), 2 vom: 01. Okt., Seite 127-142 |
|---|---|
| Übergeordnetes Werk: |
volume:1 ; year:1989 ; number:2 ; day:01 ; month:10 ; pages:127-142 |
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10.1007/BF02477178 |
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| 520 | |a Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. | ||
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10.1007/BF02477178 doi (DE-627)SPR018308236 (SPR)BF02477178-e DE-627 ger DE-627 rakwb eng Roychowdhury, V. P. verfasserin aut Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms 1989 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. Leaf Node (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Index Point (dpeaa)DE-He213 Directed Cycle (dpeaa)DE-He213 Processor Array (dpeaa)DE-He213 Kailath, T. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 1(1989), 2 vom: 01. Okt., Seite 127-142 (DE-627)SPR018308090 nnns volume:1 year:1989 number:2 day:01 month:10 pages:127-142 https://dx.doi.org/10.1007/BF02477178 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 1 1989 2 01 10 127-142 |
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10.1007/BF02477178 doi (DE-627)SPR018308236 (SPR)BF02477178-e DE-627 ger DE-627 rakwb eng Roychowdhury, V. P. verfasserin aut Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms 1989 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. Leaf Node (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Index Point (dpeaa)DE-He213 Directed Cycle (dpeaa)DE-He213 Processor Array (dpeaa)DE-He213 Kailath, T. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 1(1989), 2 vom: 01. Okt., Seite 127-142 (DE-627)SPR018308090 nnns volume:1 year:1989 number:2 day:01 month:10 pages:127-142 https://dx.doi.org/10.1007/BF02477178 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 1 1989 2 01 10 127-142 |
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10.1007/BF02477178 doi (DE-627)SPR018308236 (SPR)BF02477178-e DE-627 ger DE-627 rakwb eng Roychowdhury, V. P. verfasserin aut Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms 1989 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. Leaf Node (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Index Point (dpeaa)DE-He213 Directed Cycle (dpeaa)DE-He213 Processor Array (dpeaa)DE-He213 Kailath, T. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 1(1989), 2 vom: 01. Okt., Seite 127-142 (DE-627)SPR018308090 nnns volume:1 year:1989 number:2 day:01 month:10 pages:127-142 https://dx.doi.org/10.1007/BF02477178 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 1 1989 2 01 10 127-142 |
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10.1007/BF02477178 doi (DE-627)SPR018308236 (SPR)BF02477178-e DE-627 ger DE-627 rakwb eng Roychowdhury, V. P. verfasserin aut Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms 1989 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. Leaf Node (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Index Point (dpeaa)DE-He213 Directed Cycle (dpeaa)DE-He213 Processor Array (dpeaa)DE-He213 Kailath, T. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 1(1989), 2 vom: 01. Okt., Seite 127-142 (DE-627)SPR018308090 nnns volume:1 year:1989 number:2 day:01 month:10 pages:127-142 https://dx.doi.org/10.1007/BF02477178 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 1 1989 2 01 10 127-142 |
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10.1007/BF02477178 doi (DE-627)SPR018308236 (SPR)BF02477178-e DE-627 ger DE-627 rakwb eng Roychowdhury, V. P. verfasserin aut Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms 1989 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. Leaf Node (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Index Point (dpeaa)DE-He213 Directed Cycle (dpeaa)DE-He213 Processor Array (dpeaa)DE-He213 Kailath, T. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 1(1989), 2 vom: 01. Okt., Seite 127-142 (DE-627)SPR018308090 nnns volume:1 year:1989 number:2 day:01 month:10 pages:127-142 https://dx.doi.org/10.1007/BF02477178 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 1 1989 2 01 10 127-142 |
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subspace scheduling and parallel implementation of non-systolic regular iterative algorithms |
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Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms |
| abstract |
Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. |
| abstractGer |
Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. |
| abstract_unstemmed |
Abstract The study of Regular Iterative Algorithms (RIAs) was introduced in a seminal paper by Karp, Miller, and Winograd in 1967. In more recent years, the study of systolic architectures has led to a renewed interest in this class of algorithms, and the class of algorithms implementable on systolic arrays (as commonly understood) has been identified as a precise subclass of RIAs. In this paper, we shall study the dependence structure of RIAs that are not systolic; examples of such RIAs include matrix pivoting algorithms and certain forms of numerically stable two-dimensional filtering algorithms. It has been shown that the so-called hyperplanar scheduling for systolic algorithms can no longer be used to schedule and implement non-systolic RIAs. Based on the analysis of a so-called computability tree we generalize the concept of hyperplanar scheduling and determine linear subspaces in the index space of a given RIA such that all variables lying on the same subspace can be scheduled at the same time. This subspace scheduling technique is shown to be asymptotically optimal, and formal procedures are developed for designing processor arrays that will be compatible with our scheduling schemes. Explicit formulas for the schedule of a given variable are determined whenever possible; subspace scheduling is also applied to obtain lower dimensional processor arrays for systolic algorithms. |
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Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms |
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https://dx.doi.org/10.1007/BF02477178 |
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Kailath, T. |
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Kailath, T. |
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10.1007/BF02477178 |
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