Configurable hardware: Two case studies of micro-grain computation
Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particul...
Ausführliche Beschreibung
Autor*in: |
Kean, Tom [verfasserIn] Gray, John [verfasserIn] |
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Format: |
E-Artikel |
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Sprache: |
Englisch |
Erschienen: |
1990 |
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Schlagwörter: |
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Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 2(1990), 1 vom: 01. Sept., Seite 9-16 |
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Übergeordnetes Werk: |
volume:2 ; year:1990 ; number:1 ; day:01 ; month:09 ; pages:9-16 |
Links: |
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DOI / URN: |
10.1007/BF00931032 |
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Katalog-ID: |
SPR018308473 |
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10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
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10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
allfields_unstemmed |
10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
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10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
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10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
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Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. |
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Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. |
abstract_unstemmed |
Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. |
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Sept., Seite 9-16</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:2</subfield><subfield code="g">year:1990</subfield><subfield code="g">number:1</subfield><subfield code="g">day:01</subfield><subfield code="g">month:09</subfield><subfield code="g">pages:9-16</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF00931032</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">2</subfield><subfield code="j">1990</subfield><subfield code="e">1</subfield><subfield code="b">01</subfield><subfield code="c">09</subfield><subfield code="h">9-16</subfield></datafield></record></collection>
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