Configurable hardware: Two case studies of micro-grain computation
Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particul...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kean, Tom [verfasserIn] Gray, John [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1990 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 2(1990), 1 vom: 01. Sept., Seite 9-16 |
|---|---|
| Übergeordnetes Werk: |
volume:2 ; year:1990 ; number:1 ; day:01 ; month:09 ; pages:9-16 |
| Links: |
|---|
| DOI / URN: |
10.1007/BF00931032 |
|---|
| Katalog-ID: |
SPR018308473 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | SPR018308473 | ||
| 003 | DE-627 | ||
| 005 | 20201124222343.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 201006s1990 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1007/BF00931032 |2 doi | |
| 035 | |a (DE-627)SPR018308473 | ||
| 035 | |a (SPR)BF00931032-e | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 100 | 1 | |a Kean, Tom |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Configurable hardware: Two case studies of micro-grain computation |
| 264 | 1 | |c 1990 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 520 | |a Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. | ||
| 650 | 4 | |a Logic Gate |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Function Unit |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Systolic Array |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a String Match Algorithm |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Systolic Algorithm |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Gray, John |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Journal of VLSI signal processing systems for signal, image and video technology |d Springer Netherlands, 1989 |g 2(1990), 1 vom: 01. Sept., Seite 9-16 |w (DE-627)SPR018308090 |7 nnns |
| 773 | 1 | 8 | |g volume:2 |g year:1990 |g number:1 |g day:01 |g month:09 |g pages:9-16 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/BF00931032 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_SPRINGER | ||
| 912 | |a GBV_ILN_40 | ||
| 912 | |a GBV_ILN_2006 | ||
| 912 | |a GBV_ILN_2027 | ||
| 951 | |a AR | ||
| 952 | |d 2 |j 1990 |e 1 |b 01 |c 09 |h 9-16 | ||
| author_variant |
t k tk j g jg |
|---|---|
| matchkey_str |
keantomgrayjohn:1990----:ofgrbeadaewcssuisfirg |
| hierarchy_sort_str |
1990 |
| publishDate |
1990 |
| allfields |
10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
| spelling |
10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
| allfields_unstemmed |
10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
| allfieldsGer |
10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
| allfieldsSound |
10.1007/BF00931032 doi (DE-627)SPR018308473 (SPR)BF00931032-e DE-627 ger DE-627 rakwb eng Kean, Tom verfasserin aut Configurable hardware: Two case studies of micro-grain computation 1990 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 Gray, John verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1990), 1 vom: 01. Sept., Seite 9-16 (DE-627)SPR018308090 nnns volume:2 year:1990 number:1 day:01 month:09 pages:9-16 https://dx.doi.org/10.1007/BF00931032 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1990 1 01 09 9-16 |
| language |
English |
| source |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 2(1990), 1 vom: 01. Sept., Seite 9-16 volume:2 year:1990 number:1 day:01 month:09 pages:9-16 |
| sourceStr |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 2(1990), 1 vom: 01. Sept., Seite 9-16 volume:2 year:1990 number:1 day:01 month:09 pages:9-16 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Logic Gate Function Unit Systolic Array String Match Algorithm Systolic Algorithm |
| isfreeaccess_bool |
false |
| container_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| authorswithroles_txt_mv |
Kean, Tom @@aut@@ Gray, John @@aut@@ |
| publishDateDaySort_date |
1990-09-01T00:00:00Z |
| hierarchy_top_id |
SPR018308090 |
| id |
SPR018308473 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018308473</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222343.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1990 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF00931032</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018308473</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF00931032-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kean, Tom</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Configurable hardware: Two case studies of micro-grain computation</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1990</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic Gate</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Function Unit</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Array</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">String Match Algorithm</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Algorithm</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gray, John</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">2(1990), 1 vom: 01. Sept., Seite 9-16</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:2</subfield><subfield code="g">year:1990</subfield><subfield code="g">number:1</subfield><subfield code="g">day:01</subfield><subfield code="g">month:09</subfield><subfield code="g">pages:9-16</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF00931032</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">2</subfield><subfield code="j">1990</subfield><subfield code="e">1</subfield><subfield code="b">01</subfield><subfield code="c">09</subfield><subfield code="h">9-16</subfield></datafield></record></collection>
|
| author |
Kean, Tom |
| spellingShingle |
Kean, Tom misc Logic Gate misc Function Unit misc Systolic Array misc String Match Algorithm misc Systolic Algorithm Configurable hardware: Two case studies of micro-grain computation |
| authorStr |
Kean, Tom |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)SPR018308090 |
| format |
electronic Article |
| delete_txt_mv |
keep |
| author_role |
aut aut |
| collection |
springer |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
Configurable hardware: Two case studies of micro-grain computation Logic Gate (dpeaa)DE-He213 Function Unit (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 String Match Algorithm (dpeaa)DE-He213 Systolic Algorithm (dpeaa)DE-He213 |
| topic |
misc Logic Gate misc Function Unit misc Systolic Array misc String Match Algorithm misc Systolic Algorithm |
| topic_unstemmed |
misc Logic Gate misc Function Unit misc Systolic Array misc String Match Algorithm misc Systolic Algorithm |
| topic_browse |
misc Logic Gate misc Function Unit misc Systolic Array misc String Match Algorithm misc Systolic Algorithm |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
cr |
| hierarchy_parent_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| hierarchy_parent_id |
SPR018308090 |
| hierarchy_top_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)SPR018308090 |
| title |
Configurable hardware: Two case studies of micro-grain computation |
| ctrlnum |
(DE-627)SPR018308473 (SPR)BF00931032-e |
| title_full |
Configurable hardware: Two case studies of micro-grain computation |
| author_sort |
Kean, Tom |
| journal |
Journal of VLSI signal processing systems for signal, image and video technology |
| journalStr |
Journal of VLSI signal processing systems for signal, image and video technology |
| lang_code |
eng |
| isOA_bool |
false |
| recordtype |
marc |
| publishDateSort |
1990 |
| contenttype_str_mv |
txt |
| container_start_page |
9 |
| author_browse |
Kean, Tom Gray, John |
| container_volume |
2 |
| format_se |
Elektronische Aufsätze |
| author-letter |
Kean, Tom |
| doi_str_mv |
10.1007/BF00931032 |
| author2-role |
verfasserin |
| title_sort |
configurable hardware: two case studies of micro-grain computation |
| title_auth |
Configurable hardware: Two case studies of micro-grain computation |
| abstract |
Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. |
| abstractGer |
Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. |
| abstract_unstemmed |
Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 |
| container_issue |
1 |
| title_short |
Configurable hardware: Two case studies of micro-grain computation |
| url |
https://dx.doi.org/10.1007/BF00931032 |
| remote_bool |
true |
| author2 |
Gray, John |
| author2Str |
Gray, John |
| ppnlink |
SPR018308090 |
| mediatype_str_mv |
c |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/BF00931032 |
| up_date |
2024-07-03T18:50:21.694Z |
| _version_ |
1803584926327504896 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018308473</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222343.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1990 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF00931032</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018308473</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF00931032-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kean, Tom</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Configurable hardware: Two case studies of micro-grain computation</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1990</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper describes a new VLSI architecture—Configurable Array Logic (CAL) which, at its lowest level, can be programmed electrically to implement any circuit composed of logic gates. At higher levels the technology provides a medium for the direct implementation of algorithms. It particularly addresses systolic and cellular automaton algorithms where the basic computational elements perform computations unsuited to conventional processors.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic Gate</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Function Unit</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Array</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">String Match Algorithm</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Algorithm</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gray, John</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">2(1990), 1 vom: 01. Sept., Seite 9-16</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:2</subfield><subfield code="g">year:1990</subfield><subfield code="g">number:1</subfield><subfield code="g">day:01</subfield><subfield code="g">month:09</subfield><subfield code="g">pages:9-16</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF00931032</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">2</subfield><subfield code="j">1990</subfield><subfield code="e">1</subfield><subfield code="b">01</subfield><subfield code="c">09</subfield><subfield code="h">9-16</subfield></datafield></record></collection>
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