Comparison of tree and straight-line clocking for long systolic arrays
Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present a...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Dikaiakos, Marios D. [verfasserIn] Steiglitz, Kenneth [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1991 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 2(1991), 4 vom: 01. Mai, Seite 287-299 |
|---|---|
| Übergeordnetes Werk: |
volume:2 ; year:1991 ; number:4 ; day:01 ; month:05 ; pages:287-299 |
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| DOI / URN: |
10.1007/BF00925471 |
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| 520 | |a Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. | ||
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10.1007/BF00925471 doi (DE-627)SPR018308724 (SPR)BF00925471-e DE-627 ger DE-627 rakwb eng Dikaiakos, Marios D. verfasserin aut Comparison of tree and straight-line clocking for long systolic arrays 1991 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. Clock Signal (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Clock Period (dpeaa)DE-He213 Clock Pulse (dpeaa)DE-He213 Synchronous System (dpeaa)DE-He213 Steiglitz, Kenneth verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1991), 4 vom: 01. Mai, Seite 287-299 (DE-627)SPR018308090 nnns volume:2 year:1991 number:4 day:01 month:05 pages:287-299 https://dx.doi.org/10.1007/BF00925471 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1991 4 01 05 287-299 |
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10.1007/BF00925471 doi (DE-627)SPR018308724 (SPR)BF00925471-e DE-627 ger DE-627 rakwb eng Dikaiakos, Marios D. verfasserin aut Comparison of tree and straight-line clocking for long systolic arrays 1991 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. Clock Signal (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Clock Period (dpeaa)DE-He213 Clock Pulse (dpeaa)DE-He213 Synchronous System (dpeaa)DE-He213 Steiglitz, Kenneth verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1991), 4 vom: 01. Mai, Seite 287-299 (DE-627)SPR018308090 nnns volume:2 year:1991 number:4 day:01 month:05 pages:287-299 https://dx.doi.org/10.1007/BF00925471 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1991 4 01 05 287-299 |
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10.1007/BF00925471 doi (DE-627)SPR018308724 (SPR)BF00925471-e DE-627 ger DE-627 rakwb eng Dikaiakos, Marios D. verfasserin aut Comparison of tree and straight-line clocking for long systolic arrays 1991 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. Clock Signal (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Clock Period (dpeaa)DE-He213 Clock Pulse (dpeaa)DE-He213 Synchronous System (dpeaa)DE-He213 Steiglitz, Kenneth verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1991), 4 vom: 01. Mai, Seite 287-299 (DE-627)SPR018308090 nnns volume:2 year:1991 number:4 day:01 month:05 pages:287-299 https://dx.doi.org/10.1007/BF00925471 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1991 4 01 05 287-299 |
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10.1007/BF00925471 doi (DE-627)SPR018308724 (SPR)BF00925471-e DE-627 ger DE-627 rakwb eng Dikaiakos, Marios D. verfasserin aut Comparison of tree and straight-line clocking for long systolic arrays 1991 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. Clock Signal (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Clock Period (dpeaa)DE-He213 Clock Pulse (dpeaa)DE-He213 Synchronous System (dpeaa)DE-He213 Steiglitz, Kenneth verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1991), 4 vom: 01. Mai, Seite 287-299 (DE-627)SPR018308090 nnns volume:2 year:1991 number:4 day:01 month:05 pages:287-299 https://dx.doi.org/10.1007/BF00925471 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1991 4 01 05 287-299 |
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10.1007/BF00925471 doi (DE-627)SPR018308724 (SPR)BF00925471-e DE-627 ger DE-627 rakwb eng Dikaiakos, Marios D. verfasserin aut Comparison of tree and straight-line clocking for long systolic arrays 1991 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. Clock Signal (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Clock Period (dpeaa)DE-He213 Clock Pulse (dpeaa)DE-He213 Synchronous System (dpeaa)DE-He213 Steiglitz, Kenneth verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 2(1991), 4 vom: 01. Mai, Seite 287-299 (DE-627)SPR018308090 nnns volume:2 year:1991 number:4 day:01 month:05 pages:287-299 https://dx.doi.org/10.1007/BF00925471 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 2 1991 4 01 05 287-299 |
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Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 2(1991), 4 vom: 01. Mai, Seite 287-299 volume:2 year:1991 number:4 day:01 month:05 pages:287-299 |
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Comparison of tree and straight-line clocking for long systolic arrays |
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Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. |
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Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. |
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Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking. |
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Comparison of tree and straight-line clocking for long systolic arrays |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018308724</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222344.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1991 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF00925471</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018308724</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF00925471-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dikaiakos, Marios D.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Comparison of tree and straight-line clocking for long systolic arrays</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1991</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract A critical problem in building long systolic arrays lies in efficient and reliable synchronization. We address this problem in the context of synchronous systems by introducing probabilistic models for two alternative clock distribution schemes: tree and straight-line clocking. We present analytic bounds for the Probability of Failure and the Mean Time to Failure, and examine the trade-offs between reliability and throughput in both schemes. Our basic conclusion is that as the one-dimensional systolic array gets very long, tree clocking becomes more reliable than straight-line clocking.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Signal</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Array</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Period</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Pulse</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronous System</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Steiglitz, Kenneth</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">2(1991), 4 vom: 01. Mai, Seite 287-299</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:2</subfield><subfield code="g">year:1991</subfield><subfield code="g">number:4</subfield><subfield code="g">day:01</subfield><subfield code="g">month:05</subfield><subfield code="g">pages:287-299</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF00925471</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">2</subfield><subfield code="j">1991</subfield><subfield code="e">4</subfield><subfield code="b">01</subfield><subfield code="c">05</subfield><subfield code="h">287-299</subfield></datafield></record></collection>
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