VLSI parallel architecture for Kalman filterAn algorithm specific approach
Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are pe...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Bayoumi, Magdy A. [verfasserIn] Rao, Padma [verfasserIn] Alhalabi, Bassem [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1992 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 4(1992), 2-3 vom: 01. Mai, Seite 147-163 |
|---|---|
| Übergeordnetes Werk: |
volume:4 ; year:1992 ; number:2-3 ; day:01 ; month:05 ; pages:147-163 |
| Links: |
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| DOI / URN: |
10.1007/BF00925119 |
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SPR018309208 |
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| 520 | |a Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. | ||
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| 700 | 1 | |a Alhalabi, Bassem |e verfasserin |4 aut | |
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10.1007/BF00925119 doi (DE-627)SPR018309208 (SPR)BF00925119-e DE-627 ger DE-627 rakwb eng Bayoumi, Magdy A. verfasserin aut VLSI parallel architecture for Kalman filterAn algorithm specific approach 1992 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. Kalman Filter (dpeaa)DE-He213 Clock Cycle (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Memory Bank (dpeaa)DE-He213 VLSI Architecture (dpeaa)DE-He213 Rao, Padma verfasserin aut Alhalabi, Bassem verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 4(1992), 2-3 vom: 01. Mai, Seite 147-163 (DE-627)SPR018308090 nnns volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 https://dx.doi.org/10.1007/BF00925119 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 4 1992 2-3 01 05 147-163 |
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10.1007/BF00925119 doi (DE-627)SPR018309208 (SPR)BF00925119-e DE-627 ger DE-627 rakwb eng Bayoumi, Magdy A. verfasserin aut VLSI parallel architecture for Kalman filterAn algorithm specific approach 1992 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. Kalman Filter (dpeaa)DE-He213 Clock Cycle (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Memory Bank (dpeaa)DE-He213 VLSI Architecture (dpeaa)DE-He213 Rao, Padma verfasserin aut Alhalabi, Bassem verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 4(1992), 2-3 vom: 01. Mai, Seite 147-163 (DE-627)SPR018308090 nnns volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 https://dx.doi.org/10.1007/BF00925119 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 4 1992 2-3 01 05 147-163 |
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10.1007/BF00925119 doi (DE-627)SPR018309208 (SPR)BF00925119-e DE-627 ger DE-627 rakwb eng Bayoumi, Magdy A. verfasserin aut VLSI parallel architecture for Kalman filterAn algorithm specific approach 1992 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. Kalman Filter (dpeaa)DE-He213 Clock Cycle (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Memory Bank (dpeaa)DE-He213 VLSI Architecture (dpeaa)DE-He213 Rao, Padma verfasserin aut Alhalabi, Bassem verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 4(1992), 2-3 vom: 01. Mai, Seite 147-163 (DE-627)SPR018308090 nnns volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 https://dx.doi.org/10.1007/BF00925119 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 4 1992 2-3 01 05 147-163 |
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10.1007/BF00925119 doi (DE-627)SPR018309208 (SPR)BF00925119-e DE-627 ger DE-627 rakwb eng Bayoumi, Magdy A. verfasserin aut VLSI parallel architecture for Kalman filterAn algorithm specific approach 1992 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. Kalman Filter (dpeaa)DE-He213 Clock Cycle (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Memory Bank (dpeaa)DE-He213 VLSI Architecture (dpeaa)DE-He213 Rao, Padma verfasserin aut Alhalabi, Bassem verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 4(1992), 2-3 vom: 01. Mai, Seite 147-163 (DE-627)SPR018308090 nnns volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 https://dx.doi.org/10.1007/BF00925119 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 4 1992 2-3 01 05 147-163 |
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10.1007/BF00925119 doi (DE-627)SPR018309208 (SPR)BF00925119-e DE-627 ger DE-627 rakwb eng Bayoumi, Magdy A. verfasserin aut VLSI parallel architecture for Kalman filterAn algorithm specific approach 1992 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. Kalman Filter (dpeaa)DE-He213 Clock Cycle (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Memory Bank (dpeaa)DE-He213 VLSI Architecture (dpeaa)DE-He213 Rao, Padma verfasserin aut Alhalabi, Bassem verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 4(1992), 2-3 vom: 01. Mai, Seite 147-163 (DE-627)SPR018308090 nnns volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 https://dx.doi.org/10.1007/BF00925119 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 4 1992 2-3 01 05 147-163 |
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Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 4(1992), 2-3 vom: 01. Mai, Seite 147-163 volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 |
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Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 4(1992), 2-3 vom: 01. Mai, Seite 147-163 volume:4 year:1992 number:2-3 day:01 month:05 pages:147-163 |
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Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. |
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Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. |
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Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed. |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018309208</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222344.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1992 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF00925119</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018309208</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF00925119-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bayoumi, Magdy A.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">VLSI parallel architecture for Kalman filterAn algorithm specific approach</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1992</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract An algorithm specific architecture for Kalman filter is presented. It is based on systolic arrays. Parallelism has been exploited on both algorithm and architecture levels. Faddeev's algorithm has been employed. The involved computation tasks, triangularization and nullification are performed in parallel which leads to a speedup of about 40%. Throughput has been increased by using bi-trapezoidal arrays. Techniques have been employed for data storage and skewing which enables fast data transfer rates. A VLSI implementation of a prototype of matrix of size 4×4 has been discussed.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Kalman Filter</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Cycle</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Array</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Memory Bank</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">VLSI Architecture</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Rao, Padma</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Alhalabi, Bassem</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">4(1992), 2-3 vom: 01. Mai, Seite 147-163</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:4</subfield><subfield code="g">year:1992</subfield><subfield code="g">number:2-3</subfield><subfield code="g">day:01</subfield><subfield code="g">month:05</subfield><subfield code="g">pages:147-163</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF00925119</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">4</subfield><subfield code="j">1992</subfield><subfield code="e">2-3</subfield><subfield code="b">01</subfield><subfield code="c">05</subfield><subfield code="h">147-163</subfield></datafield></record></collection>
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