The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the i...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Schönfeld, Mirjam [verfasserIn] Franzen, Jens [verfasserIn] Schwiegershausen, Markus [verfasserIn] Pirsch, Peter [verfasserIn] Vehlies, Uwe [verfasserIn] Münzner, Andreas [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
1995 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 11(1995), 1-2 vom: 01. Okt., Seite 51-74 |
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| Übergeordnetes Werk: |
volume:11 ; year:1995 ; number:1-2 ; day:01 ; month:10 ; pages:51-74 |
| Links: |
|---|
| DOI / URN: |
10.1007/BF02106823 |
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SPR018310672 |
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| 520 | |a Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. | ||
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| 700 | 1 | |a Vehlies, Uwe |e verfasserin |4 aut | |
| 700 | 1 | |a Münzner, Andreas |e verfasserin |4 aut | |
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10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
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10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
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10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
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10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
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10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
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The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
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Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. |
| abstractGer |
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. |
| abstract_unstemmed |
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. |
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The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
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https://dx.doi.org/10.1007/BF02106823 |
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Franzen, Jens Schwiegershausen, Markus Pirsch, Peter Vehlies, Uwe Münzner, Andreas |
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Franzen, Jens Schwiegershausen, Markus Pirsch, Peter Vehlies, Uwe Münzner, Andreas |
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10.1007/BF02106823 |
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2024-07-03T18:50:52.530Z |
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