The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the i...
Ausführliche Beschreibung
Autor*in: |
Schönfeld, Mirjam [verfasserIn] Franzen, Jens [verfasserIn] Schwiegershausen, Markus [verfasserIn] Pirsch, Peter [verfasserIn] Vehlies, Uwe [verfasserIn] Münzner, Andreas [verfasserIn] |
---|
Format: |
E-Artikel |
---|---|
Sprache: |
Englisch |
Erschienen: |
1995 |
---|
Schlagwörter: |
---|
Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 11(1995), 1-2 vom: 01. Okt., Seite 51-74 |
---|---|
Übergeordnetes Werk: |
volume:11 ; year:1995 ; number:1-2 ; day:01 ; month:10 ; pages:51-74 |
Links: |
---|
DOI / URN: |
10.1007/BF02106823 |
---|
Katalog-ID: |
SPR018310672 |
---|
LEADER | 01000caa a22002652 4500 | ||
---|---|---|---|
001 | SPR018310672 | ||
003 | DE-627 | ||
005 | 20201124222346.0 | ||
007 | cr uuu---uuuuu | ||
008 | 201006s1995 xx |||||o 00| ||eng c | ||
024 | 7 | |a 10.1007/BF02106823 |2 doi | |
035 | |a (DE-627)SPR018310672 | ||
035 | |a (SPR)BF02106823-e | ||
040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
041 | |a eng | ||
100 | 1 | |a Schönfeld, Mirjam |e verfasserin |4 aut | |
245 | 1 | 4 | |a The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
264 | 1 | |c 1995 | |
336 | |a Text |b txt |2 rdacontent | ||
337 | |a Computermedien |b c |2 rdamedia | ||
338 | |a Online-Ressource |b cr |2 rdacarrier | ||
520 | |a Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. | ||
650 | 4 | |a Fault Tolerance |7 (dpeaa)DE-He213 | |
650 | 4 | |a Dependence Graph |7 (dpeaa)DE-He213 | |
650 | 4 | |a Systolic Array |7 (dpeaa)DE-He213 | |
650 | 4 | |a Symbolic Execution |7 (dpeaa)DE-He213 | |
650 | 4 | |a Array Processor |7 (dpeaa)DE-He213 | |
700 | 1 | |a Franzen, Jens |e verfasserin |4 aut | |
700 | 1 | |a Schwiegershausen, Markus |e verfasserin |4 aut | |
700 | 1 | |a Pirsch, Peter |e verfasserin |4 aut | |
700 | 1 | |a Vehlies, Uwe |e verfasserin |4 aut | |
700 | 1 | |a Münzner, Andreas |e verfasserin |4 aut | |
773 | 0 | 8 | |i Enthalten in |t Journal of VLSI signal processing systems for signal, image and video technology |d Springer Netherlands, 1989 |g 11(1995), 1-2 vom: 01. Okt., Seite 51-74 |w (DE-627)SPR018308090 |7 nnns |
773 | 1 | 8 | |g volume:11 |g year:1995 |g number:1-2 |g day:01 |g month:10 |g pages:51-74 |
856 | 4 | 0 | |u https://dx.doi.org/10.1007/BF02106823 |z lizenzpflichtig |3 Volltext |
912 | |a GBV_USEFLAG_A | ||
912 | |a SYSFLAG_A | ||
912 | |a GBV_SPRINGER | ||
912 | |a GBV_ILN_40 | ||
912 | |a GBV_ILN_2006 | ||
912 | |a GBV_ILN_2027 | ||
951 | |a AR | ||
952 | |d 11 |j 1995 |e 1-2 |b 01 |c 10 |h 51-74 |
author_variant |
m s ms j f jf m s ms p p pp u v uv a m am |
---|---|
matchkey_str |
schnfeldmirjamfranzenjensschwiegershause:1995----:hlsdsgevrnetoteyteioaryrcsosnldnmmrefrhdttaseadaltlrne |
hierarchy_sort_str |
1995 |
publishDate |
1995 |
allfields |
10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
spelling |
10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
allfields_unstemmed |
10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
allfieldsGer |
10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
allfieldsSound |
10.1007/BF02106823 doi (DE-627)SPR018310672 (SPR)BF02106823-e DE-627 ger DE-627 rakwb eng Schönfeld, Mirjam verfasserin aut The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques 1995 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 Franzen, Jens verfasserin aut Schwiegershausen, Markus verfasserin aut Pirsch, Peter verfasserin aut Vehlies, Uwe verfasserin aut Münzner, Andreas verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 11(1995), 1-2 vom: 01. Okt., Seite 51-74 (DE-627)SPR018308090 nnns volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 https://dx.doi.org/10.1007/BF02106823 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 11 1995 1-2 01 10 51-74 |
language |
English |
source |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 11(1995), 1-2 vom: 01. Okt., Seite 51-74 volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 |
sourceStr |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 11(1995), 1-2 vom: 01. Okt., Seite 51-74 volume:11 year:1995 number:1-2 day:01 month:10 pages:51-74 |
format_phy_str_mv |
Article |
institution |
findex.gbv.de |
topic_facet |
Fault Tolerance Dependence Graph Systolic Array Symbolic Execution Array Processor |
isfreeaccess_bool |
false |
container_title |
Journal of VLSI signal processing systems for signal, image and video technology |
authorswithroles_txt_mv |
Schönfeld, Mirjam @@aut@@ Franzen, Jens @@aut@@ Schwiegershausen, Markus @@aut@@ Pirsch, Peter @@aut@@ Vehlies, Uwe @@aut@@ Münzner, Andreas @@aut@@ |
publishDateDaySort_date |
1995-10-01T00:00:00Z |
hierarchy_top_id |
SPR018308090 |
id |
SPR018310672 |
language_de |
englisch |
fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018310672</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222346.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1995 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF02106823</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018310672</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF02106823-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Schönfeld, Mirjam</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="4"><subfield code="a">The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1995</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fault Tolerance</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Dependence Graph</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Array</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Symbolic Execution</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Array Processor</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Franzen, Jens</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Schwiegershausen, Markus</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Pirsch, Peter</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Vehlies, Uwe</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Münzner, Andreas</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">11(1995), 1-2 vom: 01. Okt., Seite 51-74</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:11</subfield><subfield code="g">year:1995</subfield><subfield code="g">number:1-2</subfield><subfield code="g">day:01</subfield><subfield code="g">month:10</subfield><subfield code="g">pages:51-74</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF02106823</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">11</subfield><subfield code="j">1995</subfield><subfield code="e">1-2</subfield><subfield code="b">01</subfield><subfield code="c">10</subfield><subfield code="h">51-74</subfield></datafield></record></collection>
|
author |
Schönfeld, Mirjam |
spellingShingle |
Schönfeld, Mirjam misc Fault Tolerance misc Dependence Graph misc Systolic Array misc Symbolic Execution misc Array Processor The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
authorStr |
Schönfeld, Mirjam |
ppnlink_with_tag_str_mv |
@@773@@(DE-627)SPR018308090 |
format |
electronic Article |
delete_txt_mv |
keep |
author_role |
aut aut aut aut aut aut |
collection |
springer |
remote_str |
true |
illustrated |
Not Illustrated |
topic_title |
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques Fault Tolerance (dpeaa)DE-He213 Dependence Graph (dpeaa)DE-He213 Systolic Array (dpeaa)DE-He213 Symbolic Execution (dpeaa)DE-He213 Array Processor (dpeaa)DE-He213 |
topic |
misc Fault Tolerance misc Dependence Graph misc Systolic Array misc Symbolic Execution misc Array Processor |
topic_unstemmed |
misc Fault Tolerance misc Dependence Graph misc Systolic Array misc Symbolic Execution misc Array Processor |
topic_browse |
misc Fault Tolerance misc Dependence Graph misc Systolic Array misc Symbolic Execution misc Array Processor |
format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
format_main_str_mv |
Text Zeitschrift/Artikel |
carriertype_str_mv |
cr |
hierarchy_parent_title |
Journal of VLSI signal processing systems for signal, image and video technology |
hierarchy_parent_id |
SPR018308090 |
hierarchy_top_title |
Journal of VLSI signal processing systems for signal, image and video technology |
isfreeaccess_txt |
false |
familylinks_str_mv |
(DE-627)SPR018308090 |
title |
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
ctrlnum |
(DE-627)SPR018310672 (SPR)BF02106823-e |
title_full |
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
author_sort |
Schönfeld, Mirjam |
journal |
Journal of VLSI signal processing systems for signal, image and video technology |
journalStr |
Journal of VLSI signal processing systems for signal, image and video technology |
lang_code |
eng |
isOA_bool |
false |
recordtype |
marc |
publishDateSort |
1995 |
contenttype_str_mv |
txt |
container_start_page |
51 |
author_browse |
Schönfeld, Mirjam Franzen, Jens Schwiegershausen, Markus Pirsch, Peter Vehlies, Uwe Münzner, Andreas |
container_volume |
11 |
format_se |
Elektronische Aufsätze |
author-letter |
Schönfeld, Mirjam |
doi_str_mv |
10.1007/BF02106823 |
author2-role |
verfasserin |
title_sort |
lisa design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
title_auth |
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
abstract |
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. |
abstractGer |
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. |
abstract_unstemmed |
Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability. |
collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 |
container_issue |
1-2 |
title_short |
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques |
url |
https://dx.doi.org/10.1007/BF02106823 |
remote_bool |
true |
author2 |
Franzen, Jens Schwiegershausen, Markus Pirsch, Peter Vehlies, Uwe Münzner, Andreas |
author2Str |
Franzen, Jens Schwiegershausen, Markus Pirsch, Peter Vehlies, Uwe Münzner, Andreas |
ppnlink |
SPR018308090 |
mediatype_str_mv |
c |
isOA_txt |
false |
hochschulschrift_bool |
false |
doi_str |
10.1007/BF02106823 |
up_date |
2024-07-03T18:50:52.530Z |
_version_ |
1803584958660345856 |
fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018310672</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222346.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1995 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF02106823</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018310672</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF02106823-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Schönfeld, Mirjam</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="4"><subfield code="a">The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1995</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract The LISA design environment transforms computation extensive digital signal processing algorithms into array processor architectures. It supports the complete design flow from algorithmic specification in a high-level programming language to circuit description at the gate level. From the input description a graph representation is derived by symbolic execution and further mapped onto different architectures. Netlists in different formats can be extracted using the integrated synthesis of arithmetic building blocks. For the adaptation of the architectures to external interfaces LISA includes the synthesis of intermediate memories consisting of multiport RAMs or register circuits. Another part of LISA allows the application of reconfiguration and coding techniques at different design levels to incorporate fault tolerance into both, array processors and intermediate memories. By the homogeneous representation in LISA all parts of the design process are handled in the same environment. Thus, different architectures of array processors including data transfer, control, and fault tolerance can be compared with respect to area, computation time, and reliability.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Fault Tolerance</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Dependence Graph</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systolic Array</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Symbolic Execution</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Array Processor</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Franzen, Jens</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Schwiegershausen, Markus</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Pirsch, Peter</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Vehlies, Uwe</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Münzner, Andreas</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">11(1995), 1-2 vom: 01. Okt., Seite 51-74</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:11</subfield><subfield code="g">year:1995</subfield><subfield code="g">number:1-2</subfield><subfield code="g">day:01</subfield><subfield code="g">month:10</subfield><subfield code="g">pages:51-74</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/BF02106823</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">11</subfield><subfield code="j">1995</subfield><subfield code="e">1-2</subfield><subfield code="b">01</subfield><subfield code="c">10</subfield><subfield code="h">51-74</subfield></datafield></record></collection>
|
score |
7.398983 |