Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding
Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presente...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Dick, Chris [verfasserIn] Harris, Fred [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1996 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 14(1996), 3 vom: 01. Dez., Seite 265-282 |
|---|---|
| Übergeordnetes Werk: |
volume:14 ; year:1996 ; number:3 ; day:01 ; month:12 ; pages:265-282 |
| Links: |
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| DOI / URN: |
10.1007/BF00929620 |
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| 520 | |a Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. | ||
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10.1007/BF00929620 doi (DE-627)SPR018311571 (SPR)BF00929620-e DE-627 ger DE-627 rakwb eng Dick, Chris verfasserin aut Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding 1996 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. Field Programmable Gate Array (dpeaa)DE-He213 Filter Coefficient (dpeaa)DE-He213 Distribute Arithmetic (dpeaa)DE-He213 Canonical Signed Digit (dpeaa)DE-He213 Field Programmable Gate Array Implementation (dpeaa)DE-He213 Harris, Fred verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 14(1996), 3 vom: 01. Dez., Seite 265-282 (DE-627)SPR018308090 nnns volume:14 year:1996 number:3 day:01 month:12 pages:265-282 https://dx.doi.org/10.1007/BF00929620 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 14 1996 3 01 12 265-282 |
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10.1007/BF00929620 doi (DE-627)SPR018311571 (SPR)BF00929620-e DE-627 ger DE-627 rakwb eng Dick, Chris verfasserin aut Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding 1996 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. Field Programmable Gate Array (dpeaa)DE-He213 Filter Coefficient (dpeaa)DE-He213 Distribute Arithmetic (dpeaa)DE-He213 Canonical Signed Digit (dpeaa)DE-He213 Field Programmable Gate Array Implementation (dpeaa)DE-He213 Harris, Fred verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 14(1996), 3 vom: 01. Dez., Seite 265-282 (DE-627)SPR018308090 nnns volume:14 year:1996 number:3 day:01 month:12 pages:265-282 https://dx.doi.org/10.1007/BF00929620 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 14 1996 3 01 12 265-282 |
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10.1007/BF00929620 doi (DE-627)SPR018311571 (SPR)BF00929620-e DE-627 ger DE-627 rakwb eng Dick, Chris verfasserin aut Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding 1996 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. Field Programmable Gate Array (dpeaa)DE-He213 Filter Coefficient (dpeaa)DE-He213 Distribute Arithmetic (dpeaa)DE-He213 Canonical Signed Digit (dpeaa)DE-He213 Field Programmable Gate Array Implementation (dpeaa)DE-He213 Harris, Fred verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 14(1996), 3 vom: 01. Dez., Seite 265-282 (DE-627)SPR018308090 nnns volume:14 year:1996 number:3 day:01 month:12 pages:265-282 https://dx.doi.org/10.1007/BF00929620 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 14 1996 3 01 12 265-282 |
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10.1007/BF00929620 doi (DE-627)SPR018311571 (SPR)BF00929620-e DE-627 ger DE-627 rakwb eng Dick, Chris verfasserin aut Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding 1996 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. Field Programmable Gate Array (dpeaa)DE-He213 Filter Coefficient (dpeaa)DE-He213 Distribute Arithmetic (dpeaa)DE-He213 Canonical Signed Digit (dpeaa)DE-He213 Field Programmable Gate Array Implementation (dpeaa)DE-He213 Harris, Fred verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 14(1996), 3 vom: 01. Dez., Seite 265-282 (DE-627)SPR018308090 nnns volume:14 year:1996 number:3 day:01 month:12 pages:265-282 https://dx.doi.org/10.1007/BF00929620 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 14 1996 3 01 12 265-282 |
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10.1007/BF00929620 doi (DE-627)SPR018311571 (SPR)BF00929620-e DE-627 ger DE-627 rakwb eng Dick, Chris verfasserin aut Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding 1996 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. Field Programmable Gate Array (dpeaa)DE-He213 Filter Coefficient (dpeaa)DE-He213 Distribute Arithmetic (dpeaa)DE-He213 Canonical Signed Digit (dpeaa)DE-He213 Field Programmable Gate Array Implementation (dpeaa)DE-He213 Harris, Fred verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 14(1996), 3 vom: 01. Dez., Seite 265-282 (DE-627)SPR018308090 nnns volume:14 year:1996 number:3 day:01 month:12 pages:265-282 https://dx.doi.org/10.1007/BF00929620 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 14 1996 3 01 12 265-282 |
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| abstract |
Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. |
| abstractGer |
Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. |
| abstract_unstemmed |
Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented. |
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1803584974188707840 |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018311571</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222347.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1996 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/BF00929620</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018311571</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)BF00929620-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Dick, Chris</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1996</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. 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