Clock Distribution Methodology for PowerPC™ Microprocessors
Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we d...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Ganguly, Shantanu [verfasserIn] Lehther, Daksh [verfasserIn] Pullela, Satyamurthy [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
1997 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 16(1997), 2-3 vom: 01. Juni, Seite 181-189 |
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| Übergeordnetes Werk: |
volume:16 ; year:1997 ; number:2-3 ; day:01 ; month:06 ; pages:181-189 |
| Links: |
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| DOI / URN: |
10.1023/A:1007991007969 |
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SPR018311962 |
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| 520 | |a Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. | ||
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10.1023/A:1007991007969 doi (DE-627)SPR018311962 (SPR)A:1007991007969-e DE-627 ger DE-627 rakwb eng Ganguly, Shantanu verfasserin aut Clock Distribution Methodology for PowerPC™ Microprocessors 1997 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. Central Network (dpeaa)DE-He213 Clock Signal (dpeaa)DE-He213 Clock Phase (dpeaa)DE-He213 Clock Distribution (dpeaa)DE-He213 Clock Regenerator (dpeaa)DE-He213 Lehther, Daksh verfasserin aut Pullela, Satyamurthy verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 16(1997), 2-3 vom: 01. Juni, Seite 181-189 (DE-627)SPR018308090 nnns volume:16 year:1997 number:2-3 day:01 month:06 pages:181-189 https://dx.doi.org/10.1023/A:1007991007969 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 16 1997 2-3 01 06 181-189 |
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10.1023/A:1007991007969 doi (DE-627)SPR018311962 (SPR)A:1007991007969-e DE-627 ger DE-627 rakwb eng Ganguly, Shantanu verfasserin aut Clock Distribution Methodology for PowerPC™ Microprocessors 1997 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. Central Network (dpeaa)DE-He213 Clock Signal (dpeaa)DE-He213 Clock Phase (dpeaa)DE-He213 Clock Distribution (dpeaa)DE-He213 Clock Regenerator (dpeaa)DE-He213 Lehther, Daksh verfasserin aut Pullela, Satyamurthy verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 16(1997), 2-3 vom: 01. Juni, Seite 181-189 (DE-627)SPR018308090 nnns volume:16 year:1997 number:2-3 day:01 month:06 pages:181-189 https://dx.doi.org/10.1023/A:1007991007969 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 16 1997 2-3 01 06 181-189 |
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10.1023/A:1007991007969 doi (DE-627)SPR018311962 (SPR)A:1007991007969-e DE-627 ger DE-627 rakwb eng Ganguly, Shantanu verfasserin aut Clock Distribution Methodology for PowerPC™ Microprocessors 1997 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. Central Network (dpeaa)DE-He213 Clock Signal (dpeaa)DE-He213 Clock Phase (dpeaa)DE-He213 Clock Distribution (dpeaa)DE-He213 Clock Regenerator (dpeaa)DE-He213 Lehther, Daksh verfasserin aut Pullela, Satyamurthy verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 16(1997), 2-3 vom: 01. Juni, Seite 181-189 (DE-627)SPR018308090 nnns volume:16 year:1997 number:2-3 day:01 month:06 pages:181-189 https://dx.doi.org/10.1023/A:1007991007969 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 16 1997 2-3 01 06 181-189 |
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10.1023/A:1007991007969 doi (DE-627)SPR018311962 (SPR)A:1007991007969-e DE-627 ger DE-627 rakwb eng Ganguly, Shantanu verfasserin aut Clock Distribution Methodology for PowerPC™ Microprocessors 1997 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. Central Network (dpeaa)DE-He213 Clock Signal (dpeaa)DE-He213 Clock Phase (dpeaa)DE-He213 Clock Distribution (dpeaa)DE-He213 Clock Regenerator (dpeaa)DE-He213 Lehther, Daksh verfasserin aut Pullela, Satyamurthy verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 16(1997), 2-3 vom: 01. Juni, Seite 181-189 (DE-627)SPR018308090 nnns volume:16 year:1997 number:2-3 day:01 month:06 pages:181-189 https://dx.doi.org/10.1023/A:1007991007969 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 16 1997 2-3 01 06 181-189 |
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Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. |
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Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. |
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Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems. |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018311962</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222348.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1997 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1023/A:1007991007969</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018311962</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)A:1007991007969-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ganguly, Shantanu</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Clock Distribution Methodology for PowerPC™ Microprocessors</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1997</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Central Network</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Signal</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Phase</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Distribution</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Clock Regenerator</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lehther, Daksh</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Pullela, Satyamurthy</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">16(1997), 2-3 vom: 01. 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