A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI
Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipe...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Katayama, Yoichi [verfasserIn] Kitsuki, Toshiaki [verfasserIn] Ooi, Yasushi [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1999 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 22(1999), 1 vom: 01. Aug., Seite 59-64 |
|---|---|
| Übergeordnetes Werk: |
volume:22 ; year:1999 ; number:1 ; day:01 ; month:08 ; pages:59-64 |
| Links: |
|---|
| DOI / URN: |
10.1023/A:1008173803054 |
|---|
| Katalog-ID: |
SPR018313221 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | SPR018313221 | ||
| 003 | DE-627 | ||
| 005 | 20201124222349.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 201006s1999 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1023/A:1008173803054 |2 doi | |
| 035 | |a (DE-627)SPR018313221 | ||
| 035 | |a (SPR)A:1008173803054-e | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 100 | 1 | |a Katayama, Yoichi |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI |
| 264 | 1 | |c 1999 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 520 | |a Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. | ||
| 650 | 4 | |a Discrete Cosine Transform |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Power Dissipation |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Inverse Discrete Cosine Transform |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Video Encoder |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Macro Block |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Kitsuki, Toshiaki |e verfasserin |4 aut | |
| 700 | 1 | |a Ooi, Yasushi |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Journal of VLSI signal processing systems for signal, image and video technology |d Springer Netherlands, 1989 |g 22(1999), 1 vom: 01. Aug., Seite 59-64 |w (DE-627)SPR018308090 |7 nnns |
| 773 | 1 | 8 | |g volume:22 |g year:1999 |g number:1 |g day:01 |g month:08 |g pages:59-64 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1023/A:1008173803054 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_SPRINGER | ||
| 912 | |a GBV_ILN_40 | ||
| 912 | |a GBV_ILN_2006 | ||
| 912 | |a GBV_ILN_2027 | ||
| 951 | |a AR | ||
| 952 | |d 22 |j 1999 |e 1 |b 01 |c 08 |h 59-64 | ||
| author_variant |
y k yk t k tk y o yo |
|---|---|
| matchkey_str |
katayamayoichikitsukitoshiakiooiyasushi:1999----:bokrcsigntnsnlcime2 |
| hierarchy_sort_str |
1999 |
| publishDate |
1999 |
| allfields |
10.1023/A:1008173803054 doi (DE-627)SPR018313221 (SPR)A:1008173803054-e DE-627 ger DE-627 rakwb eng Katayama, Yoichi verfasserin aut A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. Discrete Cosine Transform (dpeaa)DE-He213 Power Dissipation (dpeaa)DE-He213 Inverse Discrete Cosine Transform (dpeaa)DE-He213 Video Encoder (dpeaa)DE-He213 Macro Block (dpeaa)DE-He213 Kitsuki, Toshiaki verfasserin aut Ooi, Yasushi verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 22(1999), 1 vom: 01. Aug., Seite 59-64 (DE-627)SPR018308090 nnns volume:22 year:1999 number:1 day:01 month:08 pages:59-64 https://dx.doi.org/10.1023/A:1008173803054 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 22 1999 1 01 08 59-64 |
| spelling |
10.1023/A:1008173803054 doi (DE-627)SPR018313221 (SPR)A:1008173803054-e DE-627 ger DE-627 rakwb eng Katayama, Yoichi verfasserin aut A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. Discrete Cosine Transform (dpeaa)DE-He213 Power Dissipation (dpeaa)DE-He213 Inverse Discrete Cosine Transform (dpeaa)DE-He213 Video Encoder (dpeaa)DE-He213 Macro Block (dpeaa)DE-He213 Kitsuki, Toshiaki verfasserin aut Ooi, Yasushi verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 22(1999), 1 vom: 01. Aug., Seite 59-64 (DE-627)SPR018308090 nnns volume:22 year:1999 number:1 day:01 month:08 pages:59-64 https://dx.doi.org/10.1023/A:1008173803054 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 22 1999 1 01 08 59-64 |
| allfields_unstemmed |
10.1023/A:1008173803054 doi (DE-627)SPR018313221 (SPR)A:1008173803054-e DE-627 ger DE-627 rakwb eng Katayama, Yoichi verfasserin aut A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. Discrete Cosine Transform (dpeaa)DE-He213 Power Dissipation (dpeaa)DE-He213 Inverse Discrete Cosine Transform (dpeaa)DE-He213 Video Encoder (dpeaa)DE-He213 Macro Block (dpeaa)DE-He213 Kitsuki, Toshiaki verfasserin aut Ooi, Yasushi verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 22(1999), 1 vom: 01. Aug., Seite 59-64 (DE-627)SPR018308090 nnns volume:22 year:1999 number:1 day:01 month:08 pages:59-64 https://dx.doi.org/10.1023/A:1008173803054 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 22 1999 1 01 08 59-64 |
| allfieldsGer |
10.1023/A:1008173803054 doi (DE-627)SPR018313221 (SPR)A:1008173803054-e DE-627 ger DE-627 rakwb eng Katayama, Yoichi verfasserin aut A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. Discrete Cosine Transform (dpeaa)DE-He213 Power Dissipation (dpeaa)DE-He213 Inverse Discrete Cosine Transform (dpeaa)DE-He213 Video Encoder (dpeaa)DE-He213 Macro Block (dpeaa)DE-He213 Kitsuki, Toshiaki verfasserin aut Ooi, Yasushi verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 22(1999), 1 vom: 01. Aug., Seite 59-64 (DE-627)SPR018308090 nnns volume:22 year:1999 number:1 day:01 month:08 pages:59-64 https://dx.doi.org/10.1023/A:1008173803054 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 22 1999 1 01 08 59-64 |
| allfieldsSound |
10.1023/A:1008173803054 doi (DE-627)SPR018313221 (SPR)A:1008173803054-e DE-627 ger DE-627 rakwb eng Katayama, Yoichi verfasserin aut A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. Discrete Cosine Transform (dpeaa)DE-He213 Power Dissipation (dpeaa)DE-He213 Inverse Discrete Cosine Transform (dpeaa)DE-He213 Video Encoder (dpeaa)DE-He213 Macro Block (dpeaa)DE-He213 Kitsuki, Toshiaki verfasserin aut Ooi, Yasushi verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 22(1999), 1 vom: 01. Aug., Seite 59-64 (DE-627)SPR018308090 nnns volume:22 year:1999 number:1 day:01 month:08 pages:59-64 https://dx.doi.org/10.1023/A:1008173803054 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 22 1999 1 01 08 59-64 |
| language |
English |
| source |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 22(1999), 1 vom: 01. Aug., Seite 59-64 volume:22 year:1999 number:1 day:01 month:08 pages:59-64 |
| sourceStr |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 22(1999), 1 vom: 01. Aug., Seite 59-64 volume:22 year:1999 number:1 day:01 month:08 pages:59-64 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Discrete Cosine Transform Power Dissipation Inverse Discrete Cosine Transform Video Encoder Macro Block |
| isfreeaccess_bool |
false |
| container_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| authorswithroles_txt_mv |
Katayama, Yoichi @@aut@@ Kitsuki, Toshiaki @@aut@@ Ooi, Yasushi @@aut@@ |
| publishDateDaySort_date |
1999-08-01T00:00:00Z |
| hierarchy_top_id |
SPR018308090 |
| id |
SPR018313221 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018313221</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222349.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1999 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1023/A:1008173803054</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018313221</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)A:1008173803054-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Katayama, Yoichi</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1999</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Discrete Cosine Transform</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power Dissipation</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Inverse Discrete Cosine Transform</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Video Encoder</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Macro Block</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kitsuki, Toshiaki</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ooi, Yasushi</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">22(1999), 1 vom: 01. Aug., Seite 59-64</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:22</subfield><subfield code="g">year:1999</subfield><subfield code="g">number:1</subfield><subfield code="g">day:01</subfield><subfield code="g">month:08</subfield><subfield code="g">pages:59-64</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1023/A:1008173803054</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">22</subfield><subfield code="j">1999</subfield><subfield code="e">1</subfield><subfield code="b">01</subfield><subfield code="c">08</subfield><subfield code="h">59-64</subfield></datafield></record></collection>
|
| author |
Katayama, Yoichi |
| spellingShingle |
Katayama, Yoichi misc Discrete Cosine Transform misc Power Dissipation misc Inverse Discrete Cosine Transform misc Video Encoder misc Macro Block A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI |
| authorStr |
Katayama, Yoichi |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)SPR018308090 |
| format |
electronic Article |
| delete_txt_mv |
keep |
| author_role |
aut aut aut |
| collection |
springer |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI Discrete Cosine Transform (dpeaa)DE-He213 Power Dissipation (dpeaa)DE-He213 Inverse Discrete Cosine Transform (dpeaa)DE-He213 Video Encoder (dpeaa)DE-He213 Macro Block (dpeaa)DE-He213 |
| topic |
misc Discrete Cosine Transform misc Power Dissipation misc Inverse Discrete Cosine Transform misc Video Encoder misc Macro Block |
| topic_unstemmed |
misc Discrete Cosine Transform misc Power Dissipation misc Inverse Discrete Cosine Transform misc Video Encoder misc Macro Block |
| topic_browse |
misc Discrete Cosine Transform misc Power Dissipation misc Inverse Discrete Cosine Transform misc Video Encoder misc Macro Block |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
cr |
| hierarchy_parent_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| hierarchy_parent_id |
SPR018308090 |
| hierarchy_top_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)SPR018308090 |
| title |
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI |
| ctrlnum |
(DE-627)SPR018313221 (SPR)A:1008173803054-e |
| title_full |
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI |
| author_sort |
Katayama, Yoichi |
| journal |
Journal of VLSI signal processing systems for signal, image and video technology |
| journalStr |
Journal of VLSI signal processing systems for signal, image and video technology |
| lang_code |
eng |
| isOA_bool |
false |
| recordtype |
marc |
| publishDateSort |
1999 |
| contenttype_str_mv |
txt |
| container_start_page |
59 |
| author_browse |
Katayama, Yoichi Kitsuki, Toshiaki Ooi, Yasushi |
| container_volume |
22 |
| format_se |
Elektronische Aufsätze |
| author-letter |
Katayama, Yoichi |
| doi_str_mv |
10.1023/A:1008173803054 |
| author2-role |
verfasserin |
| title_sort |
block processing unit in a single-chip mpeg-2 video encoder lsi |
| title_auth |
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI |
| abstract |
Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. |
| abstractGer |
Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. |
| abstract_unstemmed |
Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 |
| container_issue |
1 |
| title_short |
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI |
| url |
https://dx.doi.org/10.1023/A:1008173803054 |
| remote_bool |
true |
| author2 |
Kitsuki, Toshiaki Ooi, Yasushi |
| author2Str |
Kitsuki, Toshiaki Ooi, Yasushi |
| ppnlink |
SPR018308090 |
| mediatype_str_mv |
c |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1023/A:1008173803054 |
| up_date |
2024-07-03T18:51:35.303Z |
| _version_ |
1803585003510038528 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018313221</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222349.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s1999 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1023/A:1008173803054</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018313221</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)A:1008173803054-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Katayama, Yoichi</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1999</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This paper describes a block processing unit in a single-chip MPEG-2 MPML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 μm triple-layer metal CMOS cell-base technology at 54 MHz.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Discrete Cosine Transform</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power Dissipation</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Inverse Discrete Cosine Transform</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Video Encoder</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Macro Block</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kitsuki, Toshiaki</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ooi, Yasushi</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">22(1999), 1 vom: 01. Aug., Seite 59-64</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:22</subfield><subfield code="g">year:1999</subfield><subfield code="g">number:1</subfield><subfield code="g">day:01</subfield><subfield code="g">month:08</subfield><subfield code="g">pages:59-64</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1023/A:1008173803054</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">22</subfield><subfield code="j">1999</subfield><subfield code="e">1</subfield><subfield code="b">01</subfield><subfield code="c">08</subfield><subfield code="h">59-64</subfield></datafield></record></collection>
|
| score |
7.3993473 |