Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications
Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such stre...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Milojevic, Dragomir [verfasserIn] Montperrus, Luc [verfasserIn] Verkest, Diederik [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2008 |
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| Schlagwörter: |
Multi-processor systems-on-chip (MPSoC) |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 57(2008), 2 vom: 29. Juli, Seite 139-153 |
|---|---|
| Übergeordnetes Werk: |
volume:57 ; year:2008 ; number:2 ; day:29 ; month:07 ; pages:139-153 |
| Links: |
|---|
| DOI / URN: |
10.1007/s11265-008-0251-1 |
|---|
| Katalog-ID: |
SPR018321437 |
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| 520 | |a Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. | ||
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10.1007/s11265-008-0251-1 doi (DE-627)SPR018321437 (SPR)s11265-008-0251-1-e DE-627 ger DE-627 rakwb eng Milojevic, Dragomir verfasserin aut Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. Multi-processor systems-on-chip (MPSoC) (dpeaa)DE-He213 Networks-on-chip (NoC) (dpeaa)DE-He213 Real-time video encoding, decoding (dpeaa)DE-He213 AVC/H.264 (dpeaa)DE-He213 Low-power VLSI implementation (dpeaa)DE-He213 Montperrus, Luc verfasserin aut Verkest, Diederik verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 2 vom: 29. Juli, Seite 139-153 (DE-627)SPR018308090 nnns volume:57 year:2008 number:2 day:29 month:07 pages:139-153 https://dx.doi.org/10.1007/s11265-008-0251-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 2 29 07 139-153 |
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10.1007/s11265-008-0251-1 doi (DE-627)SPR018321437 (SPR)s11265-008-0251-1-e DE-627 ger DE-627 rakwb eng Milojevic, Dragomir verfasserin aut Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. Multi-processor systems-on-chip (MPSoC) (dpeaa)DE-He213 Networks-on-chip (NoC) (dpeaa)DE-He213 Real-time video encoding, decoding (dpeaa)DE-He213 AVC/H.264 (dpeaa)DE-He213 Low-power VLSI implementation (dpeaa)DE-He213 Montperrus, Luc verfasserin aut Verkest, Diederik verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 2 vom: 29. Juli, Seite 139-153 (DE-627)SPR018308090 nnns volume:57 year:2008 number:2 day:29 month:07 pages:139-153 https://dx.doi.org/10.1007/s11265-008-0251-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 2 29 07 139-153 |
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10.1007/s11265-008-0251-1 doi (DE-627)SPR018321437 (SPR)s11265-008-0251-1-e DE-627 ger DE-627 rakwb eng Milojevic, Dragomir verfasserin aut Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. Multi-processor systems-on-chip (MPSoC) (dpeaa)DE-He213 Networks-on-chip (NoC) (dpeaa)DE-He213 Real-time video encoding, decoding (dpeaa)DE-He213 AVC/H.264 (dpeaa)DE-He213 Low-power VLSI implementation (dpeaa)DE-He213 Montperrus, Luc verfasserin aut Verkest, Diederik verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 2 vom: 29. Juli, Seite 139-153 (DE-627)SPR018308090 nnns volume:57 year:2008 number:2 day:29 month:07 pages:139-153 https://dx.doi.org/10.1007/s11265-008-0251-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 2 29 07 139-153 |
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10.1007/s11265-008-0251-1 doi (DE-627)SPR018321437 (SPR)s11265-008-0251-1-e DE-627 ger DE-627 rakwb eng Milojevic, Dragomir verfasserin aut Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. Multi-processor systems-on-chip (MPSoC) (dpeaa)DE-He213 Networks-on-chip (NoC) (dpeaa)DE-He213 Real-time video encoding, decoding (dpeaa)DE-He213 AVC/H.264 (dpeaa)DE-He213 Low-power VLSI implementation (dpeaa)DE-He213 Montperrus, Luc verfasserin aut Verkest, Diederik verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 2 vom: 29. Juli, Seite 139-153 (DE-627)SPR018308090 nnns volume:57 year:2008 number:2 day:29 month:07 pages:139-153 https://dx.doi.org/10.1007/s11265-008-0251-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 2 29 07 139-153 |
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10.1007/s11265-008-0251-1 doi (DE-627)SPR018321437 (SPR)s11265-008-0251-1-e DE-627 ger DE-627 rakwb eng Milojevic, Dragomir verfasserin aut Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. Multi-processor systems-on-chip (MPSoC) (dpeaa)DE-He213 Networks-on-chip (NoC) (dpeaa)DE-He213 Real-time video encoding, decoding (dpeaa)DE-He213 AVC/H.264 (dpeaa)DE-He213 Low-power VLSI implementation (dpeaa)DE-He213 Montperrus, Luc verfasserin aut Verkest, Diederik verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 2 vom: 29. Juli, Seite 139-153 (DE-627)SPR018308090 nnns volume:57 year:2008 number:2 day:29 month:07 pages:139-153 https://dx.doi.org/10.1007/s11265-008-0251-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 2 29 07 139-153 |
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Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications |
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Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications |
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Milojevic, Dragomir |
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Journal of VLSI signal processing systems for signal, image and video technology |
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Journal of VLSI signal processing systems for signal, image and video technology |
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2008 |
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139 |
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Milojevic, Dragomir Montperrus, Luc Verkest, Diederik |
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57 |
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Elektronische Aufsätze |
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Milojevic, Dragomir |
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10.1007/s11265-008-0251-1 |
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power dissipation of the network-on-chip in multi-processor system-on-chip dedicated for video coding applications |
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Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications |
| abstract |
Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. |
| abstractGer |
Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. |
| abstract_unstemmed |
Abstract In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%. |
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Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications |
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https://dx.doi.org/10.1007/s11265-008-0251-1 |
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Montperrus, Luc Verkest, Diederik |
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2024-07-03T18:53:54.484Z |
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