Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for...
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| Autor*in: |
Qiu, Meikang [verfasserIn] Liu, Meiqin [verfasserIn] Li, Hao [verfasserIn] Huang, Hung-Chung [verfasserIn] Li, Wenyuan [verfasserIn] Wu, Jiande [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
2008 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 57(2008), 3 vom: 04. Dez., Seite 363-379 |
|---|---|
| Übergeordnetes Werk: |
volume:57 ; year:2008 ; number:3 ; day:04 ; month:12 ; pages:363-379 |
| Links: |
|---|
| DOI / URN: |
10.1007/s11265-008-0312-5 |
|---|
| Katalog-ID: |
SPR018321593 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | SPR018321593 | ||
| 003 | DE-627 | ||
| 005 | 20201124222403.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 201006s2008 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1007/s11265-008-0312-5 |2 doi | |
| 035 | |a (DE-627)SPR018321593 | ||
| 035 | |a (SPR)s11265-008-0312-5-e | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 100 | 1 | |a Qiu, Meikang |e verfasserin |4 aut | |
| 245 | 1 | 0 | |a Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture |
| 264 | 1 | |c 2008 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 520 | |a Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. | ||
| 650 | 4 | |a Assignment |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Loop scheduling |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Multi-core |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Optimization |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Real-time |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Liu, Meiqin |e verfasserin |4 aut | |
| 700 | 1 | |a Li, Hao |e verfasserin |4 aut | |
| 700 | 1 | |a Huang, Hung-Chung |e verfasserin |4 aut | |
| 700 | 1 | |a Li, Wenyuan |e verfasserin |4 aut | |
| 700 | 1 | |a Wu, Jiande |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Journal of VLSI signal processing systems for signal, image and video technology |d Springer Netherlands, 1989 |g 57(2008), 3 vom: 04. Dez., Seite 363-379 |w (DE-627)SPR018308090 |7 nnns |
| 773 | 1 | 8 | |g volume:57 |g year:2008 |g number:3 |g day:04 |g month:12 |g pages:363-379 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/s11265-008-0312-5 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_SPRINGER | ||
| 912 | |a GBV_ILN_40 | ||
| 912 | |a GBV_ILN_2006 | ||
| 912 | |a GBV_ILN_2027 | ||
| 951 | |a AR | ||
| 952 | |d 57 |j 2008 |e 3 |b 04 |c 12 |h 363-379 | ||
| author_variant |
m q mq m l ml h l hl h c h hch w l wl j w jw |
|---|---|
| matchkey_str |
qiumeikangliumeiqinlihaohuanghungchungli:2008----:nrywrloshdlnadsinetomlioeutfnt |
| hierarchy_sort_str |
2008 |
| publishDate |
2008 |
| allfields |
10.1007/s11265-008-0312-5 doi (DE-627)SPR018321593 (SPR)s11265-008-0312-5-e DE-627 ger DE-627 rakwb eng Qiu, Meikang verfasserin aut Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. Assignment (dpeaa)DE-He213 Loop scheduling (dpeaa)DE-He213 Multi-core (dpeaa)DE-He213 Optimization (dpeaa)DE-He213 Real-time (dpeaa)DE-He213 Liu, Meiqin verfasserin aut Li, Hao verfasserin aut Huang, Hung-Chung verfasserin aut Li, Wenyuan verfasserin aut Wu, Jiande verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 3 vom: 04. Dez., Seite 363-379 (DE-627)SPR018308090 nnns volume:57 year:2008 number:3 day:04 month:12 pages:363-379 https://dx.doi.org/10.1007/s11265-008-0312-5 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 3 04 12 363-379 |
| spelling |
10.1007/s11265-008-0312-5 doi (DE-627)SPR018321593 (SPR)s11265-008-0312-5-e DE-627 ger DE-627 rakwb eng Qiu, Meikang verfasserin aut Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. Assignment (dpeaa)DE-He213 Loop scheduling (dpeaa)DE-He213 Multi-core (dpeaa)DE-He213 Optimization (dpeaa)DE-He213 Real-time (dpeaa)DE-He213 Liu, Meiqin verfasserin aut Li, Hao verfasserin aut Huang, Hung-Chung verfasserin aut Li, Wenyuan verfasserin aut Wu, Jiande verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 3 vom: 04. Dez., Seite 363-379 (DE-627)SPR018308090 nnns volume:57 year:2008 number:3 day:04 month:12 pages:363-379 https://dx.doi.org/10.1007/s11265-008-0312-5 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 3 04 12 363-379 |
| allfields_unstemmed |
10.1007/s11265-008-0312-5 doi (DE-627)SPR018321593 (SPR)s11265-008-0312-5-e DE-627 ger DE-627 rakwb eng Qiu, Meikang verfasserin aut Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. Assignment (dpeaa)DE-He213 Loop scheduling (dpeaa)DE-He213 Multi-core (dpeaa)DE-He213 Optimization (dpeaa)DE-He213 Real-time (dpeaa)DE-He213 Liu, Meiqin verfasserin aut Li, Hao verfasserin aut Huang, Hung-Chung verfasserin aut Li, Wenyuan verfasserin aut Wu, Jiande verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 3 vom: 04. Dez., Seite 363-379 (DE-627)SPR018308090 nnns volume:57 year:2008 number:3 day:04 month:12 pages:363-379 https://dx.doi.org/10.1007/s11265-008-0312-5 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 3 04 12 363-379 |
| allfieldsGer |
10.1007/s11265-008-0312-5 doi (DE-627)SPR018321593 (SPR)s11265-008-0312-5-e DE-627 ger DE-627 rakwb eng Qiu, Meikang verfasserin aut Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. Assignment (dpeaa)DE-He213 Loop scheduling (dpeaa)DE-He213 Multi-core (dpeaa)DE-He213 Optimization (dpeaa)DE-He213 Real-time (dpeaa)DE-He213 Liu, Meiqin verfasserin aut Li, Hao verfasserin aut Huang, Hung-Chung verfasserin aut Li, Wenyuan verfasserin aut Wu, Jiande verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 3 vom: 04. Dez., Seite 363-379 (DE-627)SPR018308090 nnns volume:57 year:2008 number:3 day:04 month:12 pages:363-379 https://dx.doi.org/10.1007/s11265-008-0312-5 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 3 04 12 363-379 |
| allfieldsSound |
10.1007/s11265-008-0312-5 doi (DE-627)SPR018321593 (SPR)s11265-008-0312-5-e DE-627 ger DE-627 rakwb eng Qiu, Meikang verfasserin aut Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture 2008 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. Assignment (dpeaa)DE-He213 Loop scheduling (dpeaa)DE-He213 Multi-core (dpeaa)DE-He213 Optimization (dpeaa)DE-He213 Real-time (dpeaa)DE-He213 Liu, Meiqin verfasserin aut Li, Hao verfasserin aut Huang, Hung-Chung verfasserin aut Li, Wenyuan verfasserin aut Wu, Jiande verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 57(2008), 3 vom: 04. Dez., Seite 363-379 (DE-627)SPR018308090 nnns volume:57 year:2008 number:3 day:04 month:12 pages:363-379 https://dx.doi.org/10.1007/s11265-008-0312-5 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 57 2008 3 04 12 363-379 |
| language |
English |
| source |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 57(2008), 3 vom: 04. Dez., Seite 363-379 volume:57 year:2008 number:3 day:04 month:12 pages:363-379 |
| sourceStr |
Enthalten in Journal of VLSI signal processing systems for signal, image and video technology 57(2008), 3 vom: 04. Dez., Seite 363-379 volume:57 year:2008 number:3 day:04 month:12 pages:363-379 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Assignment Loop scheduling Multi-core Optimization Real-time |
| isfreeaccess_bool |
false |
| container_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| authorswithroles_txt_mv |
Qiu, Meikang @@aut@@ Liu, Meiqin @@aut@@ Li, Hao @@aut@@ Huang, Hung-Chung @@aut@@ Li, Wenyuan @@aut@@ Wu, Jiande @@aut@@ |
| publishDateDaySort_date |
2008-12-04T00:00:00Z |
| hierarchy_top_id |
SPR018308090 |
| id |
SPR018321593 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018321593</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222403.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s2008 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s11265-008-0312-5</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018321593</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s11265-008-0312-5-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Qiu, Meikang</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2008</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Assignment</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Loop scheduling</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Multi-core</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Optimization</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Real-time</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Liu, Meiqin</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Li, Hao</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Huang, Hung-Chung</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Li, Wenyuan</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wu, Jiande</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">57(2008), 3 vom: 04. Dez., Seite 363-379</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:57</subfield><subfield code="g">year:2008</subfield><subfield code="g">number:3</subfield><subfield code="g">day:04</subfield><subfield code="g">month:12</subfield><subfield code="g">pages:363-379</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s11265-008-0312-5</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">57</subfield><subfield code="j">2008</subfield><subfield code="e">3</subfield><subfield code="b">04</subfield><subfield code="c">12</subfield><subfield code="h">363-379</subfield></datafield></record></collection>
|
| author |
Qiu, Meikang |
| spellingShingle |
Qiu, Meikang misc Assignment misc Loop scheduling misc Multi-core misc Optimization misc Real-time Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture |
| authorStr |
Qiu, Meikang |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)SPR018308090 |
| format |
electronic Article |
| delete_txt_mv |
keep |
| author_role |
aut aut aut aut aut aut |
| collection |
springer |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture Assignment (dpeaa)DE-He213 Loop scheduling (dpeaa)DE-He213 Multi-core (dpeaa)DE-He213 Optimization (dpeaa)DE-He213 Real-time (dpeaa)DE-He213 |
| topic |
misc Assignment misc Loop scheduling misc Multi-core misc Optimization misc Real-time |
| topic_unstemmed |
misc Assignment misc Loop scheduling misc Multi-core misc Optimization misc Real-time |
| topic_browse |
misc Assignment misc Loop scheduling misc Multi-core misc Optimization misc Real-time |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
cr |
| hierarchy_parent_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| hierarchy_parent_id |
SPR018308090 |
| hierarchy_top_title |
Journal of VLSI signal processing systems for signal, image and video technology |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)SPR018308090 |
| title |
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture |
| ctrlnum |
(DE-627)SPR018321593 (SPR)s11265-008-0312-5-e |
| title_full |
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture |
| author_sort |
Qiu, Meikang |
| journal |
Journal of VLSI signal processing systems for signal, image and video technology |
| journalStr |
Journal of VLSI signal processing systems for signal, image and video technology |
| lang_code |
eng |
| isOA_bool |
false |
| recordtype |
marc |
| publishDateSort |
2008 |
| contenttype_str_mv |
txt |
| container_start_page |
363 |
| author_browse |
Qiu, Meikang Liu, Meiqin Li, Hao Huang, Hung-Chung Li, Wenyuan Wu, Jiande |
| container_volume |
57 |
| format_se |
Elektronische Aufsätze |
| author-letter |
Qiu, Meikang |
| doi_str_mv |
10.1007/s11265-008-0312-5 |
| author2-role |
verfasserin |
| title_sort |
energy-aware loop scheduling and assignment for multi-core, multi-functional-unit architecture |
| title_auth |
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture |
| abstract |
Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. |
| abstractGer |
Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. |
| abstract_unstemmed |
Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction. |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 |
| container_issue |
3 |
| title_short |
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture |
| url |
https://dx.doi.org/10.1007/s11265-008-0312-5 |
| remote_bool |
true |
| author2 |
Liu, Meiqin Li, Hao Huang, Hung-Chung Li, Wenyuan Wu, Jiande |
| author2Str |
Liu, Meiqin Li, Hao Huang, Hung-Chung Li, Wenyuan Wu, Jiande |
| ppnlink |
SPR018308090 |
| mediatype_str_mv |
c |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s11265-008-0312-5 |
| up_date |
2024-07-03T18:53:57.060Z |
| _version_ |
1803585152157220865 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR018321593</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20201124222403.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201006s2008 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s11265-008-0312-5</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR018321593</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s11265-008-0312-5-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Qiu, Meikang</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2008</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract Switching activity and instruction cycles are two of the most important factors in power dissipation when the supply voltage is fixed. This paper studies the scheduling and assignment problems that minimize the total energy caused by both instruction processing and switching activities for applications with loops on multi-core, multi-Functional-Unit (multi-FU) architectures. An algorithm, EMPLS (Energy Minimization with Probability using Loop Scheduling), is proposed to minimize the total energy (E) while satisfying timing constraint (L) with guaranteed probability (P). We perform scheduling and assignment simultaneously. Our approach shows better performance than the approaches that consider scheduling and assignment in separate phases. Compared with previous work, our algorithm exhibits significant improvement in total energy reduction.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Assignment</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Loop scheduling</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Multi-core</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Optimization</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Real-time</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Liu, Meiqin</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Li, Hao</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Huang, Hung-Chung</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Li, Wenyuan</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wu, Jiande</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of VLSI signal processing systems for signal, image and video technology</subfield><subfield code="d">Springer Netherlands, 1989</subfield><subfield code="g">57(2008), 3 vom: 04. Dez., Seite 363-379</subfield><subfield code="w">(DE-627)SPR018308090</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:57</subfield><subfield code="g">year:2008</subfield><subfield code="g">number:3</subfield><subfield code="g">day:04</subfield><subfield code="g">month:12</subfield><subfield code="g">pages:363-379</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s11265-008-0312-5</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">57</subfield><subfield code="j">2008</subfield><subfield code="e">3</subfield><subfield code="b">04</subfield><subfield code="c">12</subfield><subfield code="h">363-379</subfield></datafield></record></collection>
|
| score |
7.39935 |