Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA
Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodolog...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Bariamis, Dimitris [verfasserIn] Maroulis, Dimitris [verfasserIn] Iakovidis, Dimitris K. [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2009 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 58(2009), 3 vom: 13. Mai, Seite 301-310 |
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| Übergeordnetes Werk: |
volume:58 ; year:2009 ; number:3 ; day:13 ; month:05 ; pages:301-310 |
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| DOI / URN: |
10.1007/s11265-009-0370-3 |
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SPR018321895 |
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| 520 | |a Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. | ||
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10.1007/s11265-009-0370-3 doi (DE-627)SPR018321895 (SPR)s11265-009-0370-3-e DE-627 ger DE-627 rakwb eng Bariamis, Dimitris verfasserin aut Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. Field programmable gate arrays (dpeaa)DE-He213 Digital design (dpeaa)DE-He213 Maroulis, Dimitris verfasserin aut Iakovidis, Dimitris K. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 58(2009), 3 vom: 13. Mai, Seite 301-310 (DE-627)SPR018308090 nnns volume:58 year:2009 number:3 day:13 month:05 pages:301-310 https://dx.doi.org/10.1007/s11265-009-0370-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 58 2009 3 13 05 301-310 |
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10.1007/s11265-009-0370-3 doi (DE-627)SPR018321895 (SPR)s11265-009-0370-3-e DE-627 ger DE-627 rakwb eng Bariamis, Dimitris verfasserin aut Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. Field programmable gate arrays (dpeaa)DE-He213 Digital design (dpeaa)DE-He213 Maroulis, Dimitris verfasserin aut Iakovidis, Dimitris K. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 58(2009), 3 vom: 13. Mai, Seite 301-310 (DE-627)SPR018308090 nnns volume:58 year:2009 number:3 day:13 month:05 pages:301-310 https://dx.doi.org/10.1007/s11265-009-0370-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 58 2009 3 13 05 301-310 |
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10.1007/s11265-009-0370-3 doi (DE-627)SPR018321895 (SPR)s11265-009-0370-3-e DE-627 ger DE-627 rakwb eng Bariamis, Dimitris verfasserin aut Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. Field programmable gate arrays (dpeaa)DE-He213 Digital design (dpeaa)DE-He213 Maroulis, Dimitris verfasserin aut Iakovidis, Dimitris K. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 58(2009), 3 vom: 13. Mai, Seite 301-310 (DE-627)SPR018308090 nnns volume:58 year:2009 number:3 day:13 month:05 pages:301-310 https://dx.doi.org/10.1007/s11265-009-0370-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 58 2009 3 13 05 301-310 |
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10.1007/s11265-009-0370-3 doi (DE-627)SPR018321895 (SPR)s11265-009-0370-3-e DE-627 ger DE-627 rakwb eng Bariamis, Dimitris verfasserin aut Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. Field programmable gate arrays (dpeaa)DE-He213 Digital design (dpeaa)DE-He213 Maroulis, Dimitris verfasserin aut Iakovidis, Dimitris K. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 58(2009), 3 vom: 13. Mai, Seite 301-310 (DE-627)SPR018308090 nnns volume:58 year:2009 number:3 day:13 month:05 pages:301-310 https://dx.doi.org/10.1007/s11265-009-0370-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 58 2009 3 13 05 301-310 |
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10.1007/s11265-009-0370-3 doi (DE-627)SPR018321895 (SPR)s11265-009-0370-3-e DE-627 ger DE-627 rakwb eng Bariamis, Dimitris verfasserin aut Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA 2009 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. Field programmable gate arrays (dpeaa)DE-He213 Digital design (dpeaa)DE-He213 Maroulis, Dimitris verfasserin aut Iakovidis, Dimitris K. verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 58(2009), 3 vom: 13. Mai, Seite 301-310 (DE-627)SPR018308090 nnns volume:58 year:2009 number:3 day:13 month:05 pages:301-310 https://dx.doi.org/10.1007/s11265-009-0370-3 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 58 2009 3 13 05 301-310 |
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Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. |
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Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. |
| abstract_unstemmed |
Abstract This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core. |
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Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA |
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Maroulis, Dimitris Iakovidis, Dimitris K. |
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