Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications
Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for redu...
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Gespeichert in:
| Autor*in: |
Kuang, Shiann-Rong [verfasserIn] Wu, Kun-Yi [verfasserIn] Yu, Kee-Khuan [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2012 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 72(2012), 1 vom: 21. Sept., Seite 43-55 |
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| Übergeordnetes Werk: |
volume:72 ; year:2012 ; number:1 ; day:21 ; month:09 ; pages:43-55 |
| Links: |
|---|
| DOI / URN: |
10.1007/s11265-012-0695-1 |
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| Katalog-ID: |
SPR018326293 |
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| 520 | |a Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. | ||
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| 700 | 1 | |a Wu, Kun-Yi |e verfasserin |4 aut | |
| 700 | 1 | |a Yu, Kee-Khuan |e verfasserin |4 aut | |
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10.1007/s11265-012-0695-1 doi (DE-627)SPR018326293 (SPR)s11265-012-0695-1-e DE-627 ger DE-627 rakwb eng Kuang, Shiann-Rong verfasserin aut Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications 2012 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. Multiple-precision floating-point multiplier (dpeaa)DE-He213 Iterative multiplier (dpeaa)DE-He213 Truncated multiplier (dpeaa)DE-He213 Clock gating (dpeaa)DE-He213 Wu, Kun-Yi verfasserin aut Yu, Kee-Khuan verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 72(2012), 1 vom: 21. Sept., Seite 43-55 (DE-627)SPR018308090 nnns volume:72 year:2012 number:1 day:21 month:09 pages:43-55 https://dx.doi.org/10.1007/s11265-012-0695-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 72 2012 1 21 09 43-55 |
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10.1007/s11265-012-0695-1 doi (DE-627)SPR018326293 (SPR)s11265-012-0695-1-e DE-627 ger DE-627 rakwb eng Kuang, Shiann-Rong verfasserin aut Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications 2012 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. Multiple-precision floating-point multiplier (dpeaa)DE-He213 Iterative multiplier (dpeaa)DE-He213 Truncated multiplier (dpeaa)DE-He213 Clock gating (dpeaa)DE-He213 Wu, Kun-Yi verfasserin aut Yu, Kee-Khuan verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 72(2012), 1 vom: 21. Sept., Seite 43-55 (DE-627)SPR018308090 nnns volume:72 year:2012 number:1 day:21 month:09 pages:43-55 https://dx.doi.org/10.1007/s11265-012-0695-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 72 2012 1 21 09 43-55 |
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10.1007/s11265-012-0695-1 doi (DE-627)SPR018326293 (SPR)s11265-012-0695-1-e DE-627 ger DE-627 rakwb eng Kuang, Shiann-Rong verfasserin aut Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications 2012 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. Multiple-precision floating-point multiplier (dpeaa)DE-He213 Iterative multiplier (dpeaa)DE-He213 Truncated multiplier (dpeaa)DE-He213 Clock gating (dpeaa)DE-He213 Wu, Kun-Yi verfasserin aut Yu, Kee-Khuan verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 72(2012), 1 vom: 21. Sept., Seite 43-55 (DE-627)SPR018308090 nnns volume:72 year:2012 number:1 day:21 month:09 pages:43-55 https://dx.doi.org/10.1007/s11265-012-0695-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 72 2012 1 21 09 43-55 |
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10.1007/s11265-012-0695-1 doi (DE-627)SPR018326293 (SPR)s11265-012-0695-1-e DE-627 ger DE-627 rakwb eng Kuang, Shiann-Rong verfasserin aut Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications 2012 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. Multiple-precision floating-point multiplier (dpeaa)DE-He213 Iterative multiplier (dpeaa)DE-He213 Truncated multiplier (dpeaa)DE-He213 Clock gating (dpeaa)DE-He213 Wu, Kun-Yi verfasserin aut Yu, Kee-Khuan verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 72(2012), 1 vom: 21. Sept., Seite 43-55 (DE-627)SPR018308090 nnns volume:72 year:2012 number:1 day:21 month:09 pages:43-55 https://dx.doi.org/10.1007/s11265-012-0695-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 72 2012 1 21 09 43-55 |
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10.1007/s11265-012-0695-1 doi (DE-627)SPR018326293 (SPR)s11265-012-0695-1-e DE-627 ger DE-627 rakwb eng Kuang, Shiann-Rong verfasserin aut Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications 2012 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. Multiple-precision floating-point multiplier (dpeaa)DE-He213 Iterative multiplier (dpeaa)DE-He213 Truncated multiplier (dpeaa)DE-He213 Clock gating (dpeaa)DE-He213 Wu, Kun-Yi verfasserin aut Yu, Kee-Khuan verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 72(2012), 1 vom: 21. Sept., Seite 43-55 (DE-627)SPR018308090 nnns volume:72 year:2012 number:1 day:21 month:09 pages:43-55 https://dx.doi.org/10.1007/s11265-012-0695-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 72 2012 1 21 09 43-55 |
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Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications |
| abstract |
Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. |
| abstractGer |
Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. |
| abstract_unstemmed |
Abstract Floating-point (FP) multipliers are the main energy consumers in many modern embedded digital signal processing (DSP) and multimedia systems. For lossy applications, minimizing the precision of FP multiplication operations under the acceptable accuracy loss is a well-known approach for reducing the energy consumption of FP multipliers. This paper proposes a multiple-precision FP multiplier to efficiently trade the energy consumption with the output quality. The proposed FP multiplier can perform low-precision multiplication that generates 8−, 14−, 20−, or 26-bit mantissa product through an iterative and truncated modified Booth multiplier. Energy saving for low-precision multiplication is achieved by partially suppressing the computation of mantissa multiplier. In addition, the proposed multiplier allows the bitwidth of mantissa in the multiplicand, multiplier, and output product to be dynamically changed when it performs different FP multiplication operations to further reduce energy consumption. Experimental results show that the proposed multiplier can achieve 59 %, 71 %, 73 %, and 82 % energy saving under 0.1 %, 1 %, 5 %, and 11 % accuracy loss, respectively, for the RGB-to-YUV & YUV-to-RGB conversion when compared to the conventional IEEE single-precision multiplier. In addition, the results also exhibit that the proposed multiplier can obtain more energy reduction than previous multiple-precision iterative FP multipliers. |
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| title_short |
Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications |
| url |
https://dx.doi.org/10.1007/s11265-012-0695-1 |
| remote_bool |
true |
| author2 |
Wu, Kun-Yi Yu, Kee-Khuan |
| author2Str |
Wu, Kun-Yi Yu, Kee-Khuan |
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| doi_str |
10.1007/s11265-012-0695-1 |
| up_date |
2024-07-03T18:55:17.074Z |
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| score |
7.3991976 |