Hardware Accelerators for Iris Localization
Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transfo...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Kumar, Vineet [verfasserIn] Asati, Abhijit [verfasserIn] Gupta, Anu [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2017 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Journal of VLSI signal processing systems for signal, image and video technology - Springer Netherlands, 1989, 90(2017), 4 vom: 16. Sept., Seite 655-671 |
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| Übergeordnetes Werk: |
volume:90 ; year:2017 ; number:4 ; day:16 ; month:09 ; pages:655-671 |
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| DOI / URN: |
10.1007/s11265-017-1282-2 |
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SPR018332633 |
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| 520 | |a Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. | ||
| 650 | 4 | |a Iris localization |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Iris segmentation |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Hardware accelerators |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Edge-map generation hardware |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Circular Hough transform hardware |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a FPGA implementation |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Asati, Abhijit |e verfasserin |4 aut | |
| 700 | 1 | |a Gupta, Anu |e verfasserin |4 aut | |
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10.1007/s11265-017-1282-2 doi (DE-627)SPR018332633 (SPR)s11265-017-1282-2-e DE-627 ger DE-627 rakwb eng Kumar, Vineet verfasserin aut Hardware Accelerators for Iris Localization 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. Iris localization (dpeaa)DE-He213 Iris segmentation (dpeaa)DE-He213 Hardware accelerators (dpeaa)DE-He213 Edge-map generation hardware (dpeaa)DE-He213 Circular Hough transform hardware (dpeaa)DE-He213 FPGA implementation (dpeaa)DE-He213 Asati, Abhijit verfasserin aut Gupta, Anu verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 90(2017), 4 vom: 16. Sept., Seite 655-671 (DE-627)SPR018308090 nnns volume:90 year:2017 number:4 day:16 month:09 pages:655-671 https://dx.doi.org/10.1007/s11265-017-1282-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 90 2017 4 16 09 655-671 |
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10.1007/s11265-017-1282-2 doi (DE-627)SPR018332633 (SPR)s11265-017-1282-2-e DE-627 ger DE-627 rakwb eng Kumar, Vineet verfasserin aut Hardware Accelerators for Iris Localization 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. Iris localization (dpeaa)DE-He213 Iris segmentation (dpeaa)DE-He213 Hardware accelerators (dpeaa)DE-He213 Edge-map generation hardware (dpeaa)DE-He213 Circular Hough transform hardware (dpeaa)DE-He213 FPGA implementation (dpeaa)DE-He213 Asati, Abhijit verfasserin aut Gupta, Anu verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 90(2017), 4 vom: 16. Sept., Seite 655-671 (DE-627)SPR018308090 nnns volume:90 year:2017 number:4 day:16 month:09 pages:655-671 https://dx.doi.org/10.1007/s11265-017-1282-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 90 2017 4 16 09 655-671 |
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10.1007/s11265-017-1282-2 doi (DE-627)SPR018332633 (SPR)s11265-017-1282-2-e DE-627 ger DE-627 rakwb eng Kumar, Vineet verfasserin aut Hardware Accelerators for Iris Localization 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. Iris localization (dpeaa)DE-He213 Iris segmentation (dpeaa)DE-He213 Hardware accelerators (dpeaa)DE-He213 Edge-map generation hardware (dpeaa)DE-He213 Circular Hough transform hardware (dpeaa)DE-He213 FPGA implementation (dpeaa)DE-He213 Asati, Abhijit verfasserin aut Gupta, Anu verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 90(2017), 4 vom: 16. Sept., Seite 655-671 (DE-627)SPR018308090 nnns volume:90 year:2017 number:4 day:16 month:09 pages:655-671 https://dx.doi.org/10.1007/s11265-017-1282-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 90 2017 4 16 09 655-671 |
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10.1007/s11265-017-1282-2 doi (DE-627)SPR018332633 (SPR)s11265-017-1282-2-e DE-627 ger DE-627 rakwb eng Kumar, Vineet verfasserin aut Hardware Accelerators for Iris Localization 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. Iris localization (dpeaa)DE-He213 Iris segmentation (dpeaa)DE-He213 Hardware accelerators (dpeaa)DE-He213 Edge-map generation hardware (dpeaa)DE-He213 Circular Hough transform hardware (dpeaa)DE-He213 FPGA implementation (dpeaa)DE-He213 Asati, Abhijit verfasserin aut Gupta, Anu verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 90(2017), 4 vom: 16. Sept., Seite 655-671 (DE-627)SPR018308090 nnns volume:90 year:2017 number:4 day:16 month:09 pages:655-671 https://dx.doi.org/10.1007/s11265-017-1282-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 90 2017 4 16 09 655-671 |
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10.1007/s11265-017-1282-2 doi (DE-627)SPR018332633 (SPR)s11265-017-1282-2-e DE-627 ger DE-627 rakwb eng Kumar, Vineet verfasserin aut Hardware Accelerators for Iris Localization 2017 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. Iris localization (dpeaa)DE-He213 Iris segmentation (dpeaa)DE-He213 Hardware accelerators (dpeaa)DE-He213 Edge-map generation hardware (dpeaa)DE-He213 Circular Hough transform hardware (dpeaa)DE-He213 FPGA implementation (dpeaa)DE-He213 Asati, Abhijit verfasserin aut Gupta, Anu verfasserin aut Enthalten in Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands, 1989 90(2017), 4 vom: 16. Sept., Seite 655-671 (DE-627)SPR018308090 nnns volume:90 year:2017 number:4 day:16 month:09 pages:655-671 https://dx.doi.org/10.1007/s11265-017-1282-2 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_40 GBV_ILN_2006 GBV_ILN_2027 AR 90 2017 4 16 09 655-671 |
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Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. |
| abstractGer |
Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. |
| abstract_unstemmed |
Abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. |
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Hardware Accelerators for Iris Localization |
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https://dx.doi.org/10.1007/s11265-017-1282-2 |
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Asati, Abhijit Gupta, Anu |
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10.1007/s11265-017-1282-2 |
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2024-07-03T18:57:08.950Z |
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7.400859 |