A novel approach for phase locked loop modelling using MATLAB
Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate t...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Jain, Rashmi [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2013 |
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| Schlagwörter: |
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| Anmerkung: |
© The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 |
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| Übergeordnetes Werk: |
Enthalten in: International Journal of Systems Assurance Engineering and Management - Springer-Verlag, 2010, 4(2013), 2 vom: 10. Mai, Seite 129-137 |
|---|---|
| Übergeordnetes Werk: |
volume:4 ; year:2013 ; number:2 ; day:10 ; month:05 ; pages:129-137 |
| Links: |
|---|
| DOI / URN: |
10.1007/s13198-013-0163-8 |
|---|
| Katalog-ID: |
SPR031237568 |
|---|
| LEADER | 01000caa a22002652 4500 | ||
|---|---|---|---|
| 001 | SPR031237568 | ||
| 003 | DE-627 | ||
| 005 | 20230331061307.0 | ||
| 007 | cr uuu---uuuuu | ||
| 008 | 201007s2013 xx |||||o 00| ||eng c | ||
| 024 | 7 | |a 10.1007/s13198-013-0163-8 |2 doi | |
| 035 | |a (DE-627)SPR031237568 | ||
| 035 | |a (SPR)s13198-013-0163-8-e | ||
| 040 | |a DE-627 |b ger |c DE-627 |e rakwb | ||
| 041 | |a eng | ||
| 100 | 1 | |a Jain, Rashmi |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A novel approach for phase locked loop modelling using MATLAB |
| 264 | 1 | |c 2013 | |
| 336 | |a Text |b txt |2 rdacontent | ||
| 337 | |a Computermedien |b c |2 rdamedia | ||
| 338 | |a Online-Ressource |b cr |2 rdacarrier | ||
| 500 | |a © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 | ||
| 520 | |a Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. | ||
| 650 | 4 | |a Phase locked loop |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Frequency locked loops |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Synchronisation |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Thyristor pulse |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a FACTS |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Siddiqui, Anwar S. |4 aut | |
| 700 | 1 | |a Jamil, Majid |4 aut | |
| 700 | 1 | |a Gupta, C. P. |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t International Journal of Systems Assurance Engineering and Management |d Springer-Verlag, 2010 |g 4(2013), 2 vom: 10. Mai, Seite 129-137 |w (DE-627)SPR031222420 |7 nnns |
| 773 | 1 | 8 | |g volume:4 |g year:2013 |g number:2 |g day:10 |g month:05 |g pages:129-137 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/s13198-013-0163-8 |z lizenzpflichtig |3 Volltext |
| 912 | |a GBV_USEFLAG_A | ||
| 912 | |a SYSFLAG_A | ||
| 912 | |a GBV_SPRINGER | ||
| 951 | |a AR | ||
| 952 | |d 4 |j 2013 |e 2 |b 10 |c 05 |h 129-137 | ||
| author_variant |
r j rj a s s as ass m j mj c p g cp cpg |
|---|---|
| matchkey_str |
jainrashmisiddiquianwarsjamilmajidguptac:2013----:nvlprahopaeokdopoel |
| hierarchy_sort_str |
2013 |
| publishDate |
2013 |
| allfields |
10.1007/s13198-013-0163-8 doi (DE-627)SPR031237568 (SPR)s13198-013-0163-8-e DE-627 ger DE-627 rakwb eng Jain, Rashmi verfasserin aut A novel approach for phase locked loop modelling using MATLAB 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. Phase locked loop (dpeaa)DE-He213 Frequency locked loops (dpeaa)DE-He213 Synchronisation (dpeaa)DE-He213 Thyristor pulse (dpeaa)DE-He213 FACTS (dpeaa)DE-He213 Siddiqui, Anwar S. aut Jamil, Majid aut Gupta, C. P. aut Enthalten in International Journal of Systems Assurance Engineering and Management Springer-Verlag, 2010 4(2013), 2 vom: 10. Mai, Seite 129-137 (DE-627)SPR031222420 nnns volume:4 year:2013 number:2 day:10 month:05 pages:129-137 https://dx.doi.org/10.1007/s13198-013-0163-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER AR 4 2013 2 10 05 129-137 |
| spelling |
10.1007/s13198-013-0163-8 doi (DE-627)SPR031237568 (SPR)s13198-013-0163-8-e DE-627 ger DE-627 rakwb eng Jain, Rashmi verfasserin aut A novel approach for phase locked loop modelling using MATLAB 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. Phase locked loop (dpeaa)DE-He213 Frequency locked loops (dpeaa)DE-He213 Synchronisation (dpeaa)DE-He213 Thyristor pulse (dpeaa)DE-He213 FACTS (dpeaa)DE-He213 Siddiqui, Anwar S. aut Jamil, Majid aut Gupta, C. P. aut Enthalten in International Journal of Systems Assurance Engineering and Management Springer-Verlag, 2010 4(2013), 2 vom: 10. Mai, Seite 129-137 (DE-627)SPR031222420 nnns volume:4 year:2013 number:2 day:10 month:05 pages:129-137 https://dx.doi.org/10.1007/s13198-013-0163-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER AR 4 2013 2 10 05 129-137 |
| allfields_unstemmed |
10.1007/s13198-013-0163-8 doi (DE-627)SPR031237568 (SPR)s13198-013-0163-8-e DE-627 ger DE-627 rakwb eng Jain, Rashmi verfasserin aut A novel approach for phase locked loop modelling using MATLAB 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. Phase locked loop (dpeaa)DE-He213 Frequency locked loops (dpeaa)DE-He213 Synchronisation (dpeaa)DE-He213 Thyristor pulse (dpeaa)DE-He213 FACTS (dpeaa)DE-He213 Siddiqui, Anwar S. aut Jamil, Majid aut Gupta, C. P. aut Enthalten in International Journal of Systems Assurance Engineering and Management Springer-Verlag, 2010 4(2013), 2 vom: 10. Mai, Seite 129-137 (DE-627)SPR031222420 nnns volume:4 year:2013 number:2 day:10 month:05 pages:129-137 https://dx.doi.org/10.1007/s13198-013-0163-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER AR 4 2013 2 10 05 129-137 |
| allfieldsGer |
10.1007/s13198-013-0163-8 doi (DE-627)SPR031237568 (SPR)s13198-013-0163-8-e DE-627 ger DE-627 rakwb eng Jain, Rashmi verfasserin aut A novel approach for phase locked loop modelling using MATLAB 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. Phase locked loop (dpeaa)DE-He213 Frequency locked loops (dpeaa)DE-He213 Synchronisation (dpeaa)DE-He213 Thyristor pulse (dpeaa)DE-He213 FACTS (dpeaa)DE-He213 Siddiqui, Anwar S. aut Jamil, Majid aut Gupta, C. P. aut Enthalten in International Journal of Systems Assurance Engineering and Management Springer-Verlag, 2010 4(2013), 2 vom: 10. Mai, Seite 129-137 (DE-627)SPR031222420 nnns volume:4 year:2013 number:2 day:10 month:05 pages:129-137 https://dx.doi.org/10.1007/s13198-013-0163-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER AR 4 2013 2 10 05 129-137 |
| allfieldsSound |
10.1007/s13198-013-0163-8 doi (DE-627)SPR031237568 (SPR)s13198-013-0163-8-e DE-627 ger DE-627 rakwb eng Jain, Rashmi verfasserin aut A novel approach for phase locked loop modelling using MATLAB 2013 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. Phase locked loop (dpeaa)DE-He213 Frequency locked loops (dpeaa)DE-He213 Synchronisation (dpeaa)DE-He213 Thyristor pulse (dpeaa)DE-He213 FACTS (dpeaa)DE-He213 Siddiqui, Anwar S. aut Jamil, Majid aut Gupta, C. P. aut Enthalten in International Journal of Systems Assurance Engineering and Management Springer-Verlag, 2010 4(2013), 2 vom: 10. Mai, Seite 129-137 (DE-627)SPR031222420 nnns volume:4 year:2013 number:2 day:10 month:05 pages:129-137 https://dx.doi.org/10.1007/s13198-013-0163-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER AR 4 2013 2 10 05 129-137 |
| language |
English |
| source |
Enthalten in International Journal of Systems Assurance Engineering and Management 4(2013), 2 vom: 10. Mai, Seite 129-137 volume:4 year:2013 number:2 day:10 month:05 pages:129-137 |
| sourceStr |
Enthalten in International Journal of Systems Assurance Engineering and Management 4(2013), 2 vom: 10. Mai, Seite 129-137 volume:4 year:2013 number:2 day:10 month:05 pages:129-137 |
| format_phy_str_mv |
Article |
| institution |
findex.gbv.de |
| topic_facet |
Phase locked loop Frequency locked loops Synchronisation Thyristor pulse FACTS |
| isfreeaccess_bool |
false |
| container_title |
International Journal of Systems Assurance Engineering and Management |
| authorswithroles_txt_mv |
Jain, Rashmi @@aut@@ Siddiqui, Anwar S. @@aut@@ Jamil, Majid @@aut@@ Gupta, C. P. @@aut@@ |
| publishDateDaySort_date |
2013-05-10T00:00:00Z |
| hierarchy_top_id |
SPR031222420 |
| id |
SPR031237568 |
| language_de |
englisch |
| fullrecord |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR031237568</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230331061307.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201007s2013 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s13198-013-0163-8</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR031237568</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s13198-013-0163-8-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Jain, Rashmi</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A novel approach for phase locked loop modelling using MATLAB</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2013</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loop</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Frequency locked loops</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronisation</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Thyristor pulse</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FACTS</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Siddiqui, Anwar S.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Jamil, Majid</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gupta, C. P.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">International Journal of Systems Assurance Engineering and Management</subfield><subfield code="d">Springer-Verlag, 2010</subfield><subfield code="g">4(2013), 2 vom: 10. Mai, Seite 129-137</subfield><subfield code="w">(DE-627)SPR031222420</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:4</subfield><subfield code="g">year:2013</subfield><subfield code="g">number:2</subfield><subfield code="g">day:10</subfield><subfield code="g">month:05</subfield><subfield code="g">pages:129-137</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s13198-013-0163-8</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">4</subfield><subfield code="j">2013</subfield><subfield code="e">2</subfield><subfield code="b">10</subfield><subfield code="c">05</subfield><subfield code="h">129-137</subfield></datafield></record></collection>
|
| author |
Jain, Rashmi |
| spellingShingle |
Jain, Rashmi misc Phase locked loop misc Frequency locked loops misc Synchronisation misc Thyristor pulse misc FACTS A novel approach for phase locked loop modelling using MATLAB |
| authorStr |
Jain, Rashmi |
| ppnlink_with_tag_str_mv |
@@773@@(DE-627)SPR031222420 |
| format |
electronic Article |
| delete_txt_mv |
keep |
| author_role |
aut aut aut aut |
| collection |
springer |
| remote_str |
true |
| illustrated |
Not Illustrated |
| topic_title |
A novel approach for phase locked loop modelling using MATLAB Phase locked loop (dpeaa)DE-He213 Frequency locked loops (dpeaa)DE-He213 Synchronisation (dpeaa)DE-He213 Thyristor pulse (dpeaa)DE-He213 FACTS (dpeaa)DE-He213 |
| topic |
misc Phase locked loop misc Frequency locked loops misc Synchronisation misc Thyristor pulse misc FACTS |
| topic_unstemmed |
misc Phase locked loop misc Frequency locked loops misc Synchronisation misc Thyristor pulse misc FACTS |
| topic_browse |
misc Phase locked loop misc Frequency locked loops misc Synchronisation misc Thyristor pulse misc FACTS |
| format_facet |
Elektronische Aufsätze Aufsätze Elektronische Ressource |
| format_main_str_mv |
Text Zeitschrift/Artikel |
| carriertype_str_mv |
cr |
| hierarchy_parent_title |
International Journal of Systems Assurance Engineering and Management |
| hierarchy_parent_id |
SPR031222420 |
| hierarchy_top_title |
International Journal of Systems Assurance Engineering and Management |
| isfreeaccess_txt |
false |
| familylinks_str_mv |
(DE-627)SPR031222420 |
| title |
A novel approach for phase locked loop modelling using MATLAB |
| ctrlnum |
(DE-627)SPR031237568 (SPR)s13198-013-0163-8-e |
| title_full |
A novel approach for phase locked loop modelling using MATLAB |
| author_sort |
Jain, Rashmi |
| journal |
International Journal of Systems Assurance Engineering and Management |
| journalStr |
International Journal of Systems Assurance Engineering and Management |
| lang_code |
eng |
| isOA_bool |
false |
| recordtype |
marc |
| publishDateSort |
2013 |
| contenttype_str_mv |
txt |
| container_start_page |
129 |
| author_browse |
Jain, Rashmi Siddiqui, Anwar S. Jamil, Majid Gupta, C. P. |
| container_volume |
4 |
| format_se |
Elektronische Aufsätze |
| author-letter |
Jain, Rashmi |
| doi_str_mv |
10.1007/s13198-013-0163-8 |
| title_sort |
novel approach for phase locked loop modelling using matlab |
| title_auth |
A novel approach for phase locked loop modelling using MATLAB |
| abstract |
Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 |
| abstractGer |
Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 |
| abstract_unstemmed |
Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed. © The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013 |
| collection_details |
GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER |
| container_issue |
2 |
| title_short |
A novel approach for phase locked loop modelling using MATLAB |
| url |
https://dx.doi.org/10.1007/s13198-013-0163-8 |
| remote_bool |
true |
| author2 |
Siddiqui, Anwar S. Jamil, Majid Gupta, C. P. |
| author2Str |
Siddiqui, Anwar S. Jamil, Majid Gupta, C. P. |
| ppnlink |
SPR031222420 |
| mediatype_str_mv |
c |
| isOA_txt |
false |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s13198-013-0163-8 |
| up_date |
2024-07-03T22:46:56.782Z |
| _version_ |
1803599810964488192 |
| fullrecord_marcxml |
<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR031237568</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230331061307.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201007s2013 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s13198-013-0163-8</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR031237568</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s13198-013-0163-8-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Jain, Rashmi</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A novel approach for phase locked loop modelling using MATLAB</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2013</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© The Society for Reliability Engineering, Quality and Operations Management (SREQOM), India and The Division of Operation and Maintenance, Lulea University of Technology, Sweden 2013</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This research aims at the special needs of phase locked loops (PLLs) for a typical application with FACTS devices. An adaptive PLL system comprising of three independent control units i.e. frequency, phase angle and voltage magnitude has been proposed. The output angle is used to generate the synchronised pulses for thyristors in FACTS devices which control the operation of these devices. The proposed controller reduces the phase and frequency error efficiently. The stability of the system is also increased even transient disturbances occurred in the system. In this paper, the design of proposed adaptive PLL is suggested using MATLAB, Simulink as a simulation tool. The total harmonics distortion are calculated in case a fault occurs in the system and compared with that of the system without any fault. The simulation results are simulated using MATLAB block-set and noticeable improvements are discussed.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase locked loop</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Frequency locked loops</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Synchronisation</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Thyristor pulse</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FACTS</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Siddiqui, Anwar S.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Jamil, Majid</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gupta, C. P.</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">International Journal of Systems Assurance Engineering and Management</subfield><subfield code="d">Springer-Verlag, 2010</subfield><subfield code="g">4(2013), 2 vom: 10. Mai, Seite 129-137</subfield><subfield code="w">(DE-627)SPR031222420</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:4</subfield><subfield code="g">year:2013</subfield><subfield code="g">number:2</subfield><subfield code="g">day:10</subfield><subfield code="g">month:05</subfield><subfield code="g">pages:129-137</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s13198-013-0163-8</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">4</subfield><subfield code="j">2013</subfield><subfield code="e">2</subfield><subfield code="b">10</subfield><subfield code="c">05</subfield><subfield code="h">129-137</subfield></datafield></record></collection>
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