Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation
Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Nogueira, Gabriel Leonardo [verfasserIn] da Silva Ozório, Maiza [verfasserIn] da Silva, Marcelo Marques [verfasserIn] Morais, Rogério Miranda [verfasserIn] Alves, Neri [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2018 |
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| Schlagwörter: |
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| Übergeordnetes Werk: |
Enthalten in: Electronic materials letters - Berlin : Springer, 2009, 14(2018), 3 vom: 14. März, Seite 319-327 |
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| Übergeordnetes Werk: |
volume:14 ; year:2018 ; number:3 ; day:14 ; month:03 ; pages:319-327 |
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| DOI / URN: |
10.1007/s13391-018-0034-1 |
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| Katalog-ID: |
SPR031564909 |
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| 245 | 1 | 0 | |a Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation |
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| 520 | |a Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract | ||
| 650 | 4 | |a Vertical transistor |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Permeable electrode |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a AL |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a O |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a /PMMA |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Thermal evaporation |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a da Silva Ozório, Maiza |e verfasserin |4 aut | |
| 700 | 1 | |a da Silva, Marcelo Marques |e verfasserin |4 aut | |
| 700 | 1 | |a Morais, Rogério Miranda |e verfasserin |4 aut | |
| 700 | 1 | |a Alves, Neri |e verfasserin |4 aut | |
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| 773 | 1 | 8 | |g volume:14 |g year:2018 |g number:3 |g day:14 |g month:03 |g pages:319-327 |
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10.1007/s13391-018-0034-1 doi (DE-627)SPR031564909 (SPR)s13391-018-0034-1-e DE-627 ger DE-627 rakwb eng 620 660 670 ASE Nogueira, Gabriel Leonardo verfasserin aut Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract Vertical transistor (dpeaa)DE-He213 Permeable electrode (dpeaa)DE-He213 AL (dpeaa)DE-He213 O (dpeaa)DE-He213 /PMMA (dpeaa)DE-He213 Thermal evaporation (dpeaa)DE-He213 da Silva Ozório, Maiza verfasserin aut da Silva, Marcelo Marques verfasserin aut Morais, Rogério Miranda verfasserin aut Alves, Neri verfasserin aut Enthalten in Electronic materials letters Berlin : Springer, 2009 14(2018), 3 vom: 14. März, Seite 319-327 (DE-627)656497157 (DE-600)2604508-4 2093-6788 nnns volume:14 year:2018 number:3 day:14 month:03 pages:319-327 https://dx.doi.org/10.1007/s13391-018-0034-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OLC-PHA GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 14 2018 3 14 03 319-327 |
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10.1007/s13391-018-0034-1 doi (DE-627)SPR031564909 (SPR)s13391-018-0034-1-e DE-627 ger DE-627 rakwb eng 620 660 670 ASE Nogueira, Gabriel Leonardo verfasserin aut Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract Vertical transistor (dpeaa)DE-He213 Permeable electrode (dpeaa)DE-He213 AL (dpeaa)DE-He213 O (dpeaa)DE-He213 /PMMA (dpeaa)DE-He213 Thermal evaporation (dpeaa)DE-He213 da Silva Ozório, Maiza verfasserin aut da Silva, Marcelo Marques verfasserin aut Morais, Rogério Miranda verfasserin aut Alves, Neri verfasserin aut Enthalten in Electronic materials letters Berlin : Springer, 2009 14(2018), 3 vom: 14. März, Seite 319-327 (DE-627)656497157 (DE-600)2604508-4 2093-6788 nnns volume:14 year:2018 number:3 day:14 month:03 pages:319-327 https://dx.doi.org/10.1007/s13391-018-0034-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OLC-PHA GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 14 2018 3 14 03 319-327 |
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10.1007/s13391-018-0034-1 doi (DE-627)SPR031564909 (SPR)s13391-018-0034-1-e DE-627 ger DE-627 rakwb eng 620 660 670 ASE Nogueira, Gabriel Leonardo verfasserin aut Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract Vertical transistor (dpeaa)DE-He213 Permeable electrode (dpeaa)DE-He213 AL (dpeaa)DE-He213 O (dpeaa)DE-He213 /PMMA (dpeaa)DE-He213 Thermal evaporation (dpeaa)DE-He213 da Silva Ozório, Maiza verfasserin aut da Silva, Marcelo Marques verfasserin aut Morais, Rogério Miranda verfasserin aut Alves, Neri verfasserin aut Enthalten in Electronic materials letters Berlin : Springer, 2009 14(2018), 3 vom: 14. März, Seite 319-327 (DE-627)656497157 (DE-600)2604508-4 2093-6788 nnns volume:14 year:2018 number:3 day:14 month:03 pages:319-327 https://dx.doi.org/10.1007/s13391-018-0034-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OLC-PHA GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 14 2018 3 14 03 319-327 |
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10.1007/s13391-018-0034-1 doi (DE-627)SPR031564909 (SPR)s13391-018-0034-1-e DE-627 ger DE-627 rakwb eng 620 660 670 ASE Nogueira, Gabriel Leonardo verfasserin aut Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract Vertical transistor (dpeaa)DE-He213 Permeable electrode (dpeaa)DE-He213 AL (dpeaa)DE-He213 O (dpeaa)DE-He213 /PMMA (dpeaa)DE-He213 Thermal evaporation (dpeaa)DE-He213 da Silva Ozório, Maiza verfasserin aut da Silva, Marcelo Marques verfasserin aut Morais, Rogério Miranda verfasserin aut Alves, Neri verfasserin aut Enthalten in Electronic materials letters Berlin : Springer, 2009 14(2018), 3 vom: 14. März, Seite 319-327 (DE-627)656497157 (DE-600)2604508-4 2093-6788 nnns volume:14 year:2018 number:3 day:14 month:03 pages:319-327 https://dx.doi.org/10.1007/s13391-018-0034-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OLC-PHA GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 14 2018 3 14 03 319-327 |
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10.1007/s13391-018-0034-1 doi (DE-627)SPR031564909 (SPR)s13391-018-0034-1-e DE-627 ger DE-627 rakwb eng 620 660 670 ASE Nogueira, Gabriel Leonardo verfasserin aut Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract Vertical transistor (dpeaa)DE-He213 Permeable electrode (dpeaa)DE-He213 AL (dpeaa)DE-He213 O (dpeaa)DE-He213 /PMMA (dpeaa)DE-He213 Thermal evaporation (dpeaa)DE-He213 da Silva Ozório, Maiza verfasserin aut da Silva, Marcelo Marques verfasserin aut Morais, Rogério Miranda verfasserin aut Alves, Neri verfasserin aut Enthalten in Electronic materials letters Berlin : Springer, 2009 14(2018), 3 vom: 14. März, Seite 319-327 (DE-627)656497157 (DE-600)2604508-4 2093-6788 nnns volume:14 year:2018 number:3 day:14 month:03 pages:319-327 https://dx.doi.org/10.1007/s13391-018-0034-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OLC-PHA GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2070 GBV_ILN_2086 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2116 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 14 2018 3 14 03 319-327 |
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Enthalten in Electronic materials letters 14(2018), 3 vom: 14. März, Seite 319-327 volume:14 year:2018 number:3 day:14 month:03 pages:319-327 |
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Enthalten in Electronic materials letters 14(2018), 3 vom: 14. März, Seite 319-327 volume:14 year:2018 number:3 day:14 month:03 pages:319-327 |
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Vertical transistor Permeable electrode AL O /PMMA Thermal evaporation |
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Nogueira, Gabriel Leonardo @@aut@@ da Silva Ozório, Maiza @@aut@@ da Silva, Marcelo Marques @@aut@@ Morais, Rogério Miranda @@aut@@ Alves, Neri @@aut@@ |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR031564909</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230519155611.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201007s2018 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s13391-018-0034-1</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR031564909</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s13391-018-0034-1-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">620</subfield><subfield code="a">660</subfield><subfield code="a">670</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Nogueira, Gabriel Leonardo</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2018</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. 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Nogueira, Gabriel Leonardo |
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Nogueira, Gabriel Leonardo ddc 620 misc Vertical transistor misc Permeable electrode misc AL misc O misc /PMMA misc Thermal evaporation Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation |
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620 660 670 ASE Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation Vertical transistor (dpeaa)DE-He213 Permeable electrode (dpeaa)DE-He213 AL (dpeaa)DE-He213 O (dpeaa)DE-He213 /PMMA (dpeaa)DE-He213 Thermal evaporation (dpeaa)DE-He213 |
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ddc 620 misc Vertical transistor misc Permeable electrode misc AL misc O misc /PMMA misc Thermal evaporation |
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Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation |
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Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation |
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Nogueira, Gabriel Leonardo da Silva Ozório, Maiza da Silva, Marcelo Marques Morais, Rogério Miranda Alves, Neri |
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middle electrode in a vertical transistor structure using an sn layer by thermal evaporation |
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Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation |
| abstract |
Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract |
| abstractGer |
Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract |
| abstract_unstemmed |
Abstract We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide ($ Al_{2} %$ O_{3} $), obtained by anodization, and $ Al_{2} %$ O_{3} $ covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare $ Al_{2} %$ O_{3} $. The addition of a PMMA layer on the $ Al_{2} %$ O_{3} $ surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, $ V_{TH} $ = − 8 V and $ E_{TH} $ = 354.5 MV/m respectively, were calculated using an $ Al_{2} %$ O_{3} $ film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare $ Al_{2} %$ O_{3} $ these values were $ V_{TH} $ = − 10 V and $ E_{TH} $ = 500 MV/m. Graphical Abstract |
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3 |
| title_short |
Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation |
| url |
https://dx.doi.org/10.1007/s13391-018-0034-1 |
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| author2 |
da Silva Ozório, Maiza da Silva, Marcelo Marques Morais, Rogério Miranda Alves, Neri |
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da Silva Ozório, Maiza da Silva, Marcelo Marques Morais, Rogério Miranda Alves, Neri |
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| doi_str |
10.1007/s13391-018-0034-1 |
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2024-07-04T00:18:55.834Z |
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| score |
7.399905 |