Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system
Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satell...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Gupta, Rupal [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2018 |
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| Schlagwörter: |
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| Anmerkung: |
© Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 |
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| Übergeordnetes Werk: |
Enthalten in: International journal of information technology - [Singapore] : Springer Singapore, 2017, 11(2018), 2 vom: 19. Juli, Seite 331-340 |
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| Übergeordnetes Werk: |
volume:11 ; year:2018 ; number:2 ; day:19 ; month:07 ; pages:331-340 |
| Links: |
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| DOI / URN: |
10.1007/s41870-018-0219-8 |
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| Katalog-ID: |
SPR038324350 |
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| 100 | 1 | |a Gupta, Rupal |e verfasserin |0 (orcid)0000-0002-2485-337X |4 aut | |
| 245 | 1 | 0 | |a Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system |
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| 520 | |a Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. | ||
| 650 | 4 | |a AIS |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a S-AIS |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a FPGA |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Protocols |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a I2C bus |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a MIL 1553 bus |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Bus controller |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Remote controller |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Kumar, Adesh |4 aut | |
| 700 | 1 | |a Sahay, Gaurangi |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t International journal of information technology |d [Singapore] : Springer Singapore, 2017 |g 11(2018), 2 vom: 19. Juli, Seite 331-340 |w (DE-627)87523142X |w (DE-600)2878562-9 |x 2511-2112 |7 nnns |
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10.1007/s41870-018-0219-8 doi (DE-627)SPR038324350 (SPR)s41870-018-0219-8-e DE-627 ger DE-627 rakwb eng Gupta, Rupal verfasserin (orcid)0000-0002-2485-337X aut Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. AIS (dpeaa)DE-He213 S-AIS (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 Protocols (dpeaa)DE-He213 I2C bus (dpeaa)DE-He213 MIL 1553 bus (dpeaa)DE-He213 Bus controller (dpeaa)DE-He213 Remote controller (dpeaa)DE-He213 Kumar, Adesh aut Sahay, Gaurangi aut Enthalten in International journal of information technology [Singapore] : Springer Singapore, 2017 11(2018), 2 vom: 19. Juli, Seite 331-340 (DE-627)87523142X (DE-600)2878562-9 2511-2112 nnns volume:11 year:2018 number:2 day:19 month:07 pages:331-340 https://dx.doi.org/10.1007/s41870-018-0219-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_266 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 11 2018 2 19 07 331-340 |
| spelling |
10.1007/s41870-018-0219-8 doi (DE-627)SPR038324350 (SPR)s41870-018-0219-8-e DE-627 ger DE-627 rakwb eng Gupta, Rupal verfasserin (orcid)0000-0002-2485-337X aut Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. AIS (dpeaa)DE-He213 S-AIS (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 Protocols (dpeaa)DE-He213 I2C bus (dpeaa)DE-He213 MIL 1553 bus (dpeaa)DE-He213 Bus controller (dpeaa)DE-He213 Remote controller (dpeaa)DE-He213 Kumar, Adesh aut Sahay, Gaurangi aut Enthalten in International journal of information technology [Singapore] : Springer Singapore, 2017 11(2018), 2 vom: 19. Juli, Seite 331-340 (DE-627)87523142X (DE-600)2878562-9 2511-2112 nnns volume:11 year:2018 number:2 day:19 month:07 pages:331-340 https://dx.doi.org/10.1007/s41870-018-0219-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_266 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 11 2018 2 19 07 331-340 |
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10.1007/s41870-018-0219-8 doi (DE-627)SPR038324350 (SPR)s41870-018-0219-8-e DE-627 ger DE-627 rakwb eng Gupta, Rupal verfasserin (orcid)0000-0002-2485-337X aut Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. AIS (dpeaa)DE-He213 S-AIS (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 Protocols (dpeaa)DE-He213 I2C bus (dpeaa)DE-He213 MIL 1553 bus (dpeaa)DE-He213 Bus controller (dpeaa)DE-He213 Remote controller (dpeaa)DE-He213 Kumar, Adesh aut Sahay, Gaurangi aut Enthalten in International journal of information technology [Singapore] : Springer Singapore, 2017 11(2018), 2 vom: 19. Juli, Seite 331-340 (DE-627)87523142X (DE-600)2878562-9 2511-2112 nnns volume:11 year:2018 number:2 day:19 month:07 pages:331-340 https://dx.doi.org/10.1007/s41870-018-0219-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_266 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 11 2018 2 19 07 331-340 |
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10.1007/s41870-018-0219-8 doi (DE-627)SPR038324350 (SPR)s41870-018-0219-8-e DE-627 ger DE-627 rakwb eng Gupta, Rupal verfasserin (orcid)0000-0002-2485-337X aut Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. AIS (dpeaa)DE-He213 S-AIS (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 Protocols (dpeaa)DE-He213 I2C bus (dpeaa)DE-He213 MIL 1553 bus (dpeaa)DE-He213 Bus controller (dpeaa)DE-He213 Remote controller (dpeaa)DE-He213 Kumar, Adesh aut Sahay, Gaurangi aut Enthalten in International journal of information technology [Singapore] : Springer Singapore, 2017 11(2018), 2 vom: 19. Juli, Seite 331-340 (DE-627)87523142X (DE-600)2878562-9 2511-2112 nnns volume:11 year:2018 number:2 day:19 month:07 pages:331-340 https://dx.doi.org/10.1007/s41870-018-0219-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_266 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 11 2018 2 19 07 331-340 |
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10.1007/s41870-018-0219-8 doi (DE-627)SPR038324350 (SPR)s41870-018-0219-8-e DE-627 ger DE-627 rakwb eng Gupta, Rupal verfasserin (orcid)0000-0002-2485-337X aut Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system 2018 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. AIS (dpeaa)DE-He213 S-AIS (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 Protocols (dpeaa)DE-He213 I2C bus (dpeaa)DE-He213 MIL 1553 bus (dpeaa)DE-He213 Bus controller (dpeaa)DE-He213 Remote controller (dpeaa)DE-He213 Kumar, Adesh aut Sahay, Gaurangi aut Enthalten in International journal of information technology [Singapore] : Springer Singapore, 2017 11(2018), 2 vom: 19. Juli, Seite 331-340 (DE-627)87523142X (DE-600)2878562-9 2511-2112 nnns volume:11 year:2018 number:2 day:19 month:07 pages:331-340 https://dx.doi.org/10.1007/s41870-018-0219-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_266 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 11 2018 2 19 07 331-340 |
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Enthalten in International journal of information technology 11(2018), 2 vom: 19. Juli, Seite 331-340 volume:11 year:2018 number:2 day:19 month:07 pages:331-340 |
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Gupta, Rupal @@aut@@ Kumar, Adesh @@aut@@ Sahay, Gaurangi @@aut@@ |
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The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. 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Gupta, Rupal |
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Gupta, Rupal misc AIS misc S-AIS misc FPGA misc Protocols misc I2C bus misc MIL 1553 bus misc Bus controller misc Remote controller Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system |
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Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system AIS (dpeaa)DE-He213 S-AIS (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 Protocols (dpeaa)DE-He213 I2C bus (dpeaa)DE-He213 MIL 1553 bus (dpeaa)DE-He213 Bus controller (dpeaa)DE-He213 Remote controller (dpeaa)DE-He213 |
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misc AIS misc S-AIS misc FPGA misc Protocols misc I2C bus misc MIL 1553 bus misc Bus controller misc Remote controller |
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Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system |
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Gupta, Rupal Kumar, Adesh Sahay, Gaurangi |
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design and implementation of i2c interface on fpga for space borne ais receiver in embedded system |
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Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system |
| abstract |
Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 |
| abstractGer |
Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 |
| abstract_unstemmed |
Abstract This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT. © Bharati Vidyapeeth's Institute of Computer Applications and Management 2018 |
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| title_short |
Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system |
| url |
https://dx.doi.org/10.1007/s41870-018-0219-8 |
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true |
| author2 |
Kumar, Adesh Sahay, Gaurangi |
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Kumar, Adesh Sahay, Gaurangi |
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87523142X |
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| doi_str |
10.1007/s41870-018-0219-8 |
| up_date |
2024-07-03T17:24:57.368Z |
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1803579553081196545 |
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| score |
7.4011936 |