Wireline communication: the backbone of data transfer

Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the m...
Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Saxena, Saurabh [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2020

Schlagwörter:	Voltage-mode output driver Digital CDR Equalization Channel loss

Übergeordnetes Werk:	Enthalten in: CSI transactions on ICT - New Delhi : Springer India, 2013, 8(2020), 2 vom: Juni, Seite 147-156
Übergeordnetes Werk:	volume:8 ; year:2020 ; number:2 ; month:06 ; pages:147-156

Links:	Volltext

DOI / URN:	10.1007/s40012-020-00297-1

Katalog-ID:	SPR040342395

Internformat


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520			\|a Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
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Indexfelder

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publishDate	2020
allfields	10.1007/s40012-020-00297-1 doi (DE-627)SPR040342395 (SPR)s40012-020-00297-1-e DE-627 ger DE-627 rakwb eng 004 ASE Saxena, Saurabh verfasserin aut Wireline communication: the backbone of data transfer 2020 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed. Voltage-mode output driver (dpeaa)DE-He213 Digital CDR (dpeaa)DE-He213 Equalization (dpeaa)DE-He213 Channel loss (dpeaa)DE-He213 Enthalten in CSI transactions on ICT New Delhi : Springer India, 2013 8(2020), 2 vom: Juni, Seite 147-156 (DE-627)736559264 (DE-600)2703329-6 2277-9086 nnns volume:8 year:2020 number:2 month:06 pages:147-156 https://dx.doi.org/10.1007/s40012-020-00297-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 8 2020 2 06 147-156
spelling	10.1007/s40012-020-00297-1 doi (DE-627)SPR040342395 (SPR)s40012-020-00297-1-e DE-627 ger DE-627 rakwb eng 004 ASE Saxena, Saurabh verfasserin aut Wireline communication: the backbone of data transfer 2020 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed. Voltage-mode output driver (dpeaa)DE-He213 Digital CDR (dpeaa)DE-He213 Equalization (dpeaa)DE-He213 Channel loss (dpeaa)DE-He213 Enthalten in CSI transactions on ICT New Delhi : Springer India, 2013 8(2020), 2 vom: Juni, Seite 147-156 (DE-627)736559264 (DE-600)2703329-6 2277-9086 nnns volume:8 year:2020 number:2 month:06 pages:147-156 https://dx.doi.org/10.1007/s40012-020-00297-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 8 2020 2 06 147-156
allfields_unstemmed	10.1007/s40012-020-00297-1 doi (DE-627)SPR040342395 (SPR)s40012-020-00297-1-e DE-627 ger DE-627 rakwb eng 004 ASE Saxena, Saurabh verfasserin aut Wireline communication: the backbone of data transfer 2020 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed. Voltage-mode output driver (dpeaa)DE-He213 Digital CDR (dpeaa)DE-He213 Equalization (dpeaa)DE-He213 Channel loss (dpeaa)DE-He213 Enthalten in CSI transactions on ICT New Delhi : Springer India, 2013 8(2020), 2 vom: Juni, Seite 147-156 (DE-627)736559264 (DE-600)2703329-6 2277-9086 nnns volume:8 year:2020 number:2 month:06 pages:147-156 https://dx.doi.org/10.1007/s40012-020-00297-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 8 2020 2 06 147-156
allfieldsGer	10.1007/s40012-020-00297-1 doi (DE-627)SPR040342395 (SPR)s40012-020-00297-1-e DE-627 ger DE-627 rakwb eng 004 ASE Saxena, Saurabh verfasserin aut Wireline communication: the backbone of data transfer 2020 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed. Voltage-mode output driver (dpeaa)DE-He213 Digital CDR (dpeaa)DE-He213 Equalization (dpeaa)DE-He213 Channel loss (dpeaa)DE-He213 Enthalten in CSI transactions on ICT New Delhi : Springer India, 2013 8(2020), 2 vom: Juni, Seite 147-156 (DE-627)736559264 (DE-600)2703329-6 2277-9086 nnns volume:8 year:2020 number:2 month:06 pages:147-156 https://dx.doi.org/10.1007/s40012-020-00297-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 8 2020 2 06 147-156
allfieldsSound	10.1007/s40012-020-00297-1 doi (DE-627)SPR040342395 (SPR)s40012-020-00297-1-e DE-627 ger DE-627 rakwb eng 004 ASE Saxena, Saurabh verfasserin aut Wireline communication: the backbone of data transfer 2020 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed. Voltage-mode output driver (dpeaa)DE-He213 Digital CDR (dpeaa)DE-He213 Equalization (dpeaa)DE-He213 Channel loss (dpeaa)DE-He213 Enthalten in CSI transactions on ICT New Delhi : Springer India, 2013 8(2020), 2 vom: Juni, Seite 147-156 (DE-627)736559264 (DE-600)2703329-6 2277-9086 nnns volume:8 year:2020 number:2 month:06 pages:147-156 https://dx.doi.org/10.1007/s40012-020-00297-1 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 8 2020 2 06 147-156
language	English
source	Enthalten in CSI transactions on ICT 8(2020), 2 vom: Juni, Seite 147-156 volume:8 year:2020 number:2 month:06 pages:147-156
sourceStr	Enthalten in CSI transactions on ICT 8(2020), 2 vom: Juni, Seite 147-156 volume:8 year:2020 number:2 month:06 pages:147-156
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Voltage-mode output driver Digital CDR Equalization Channel loss
dewey-raw	004
isfreeaccess_bool	false
container_title	CSI transactions on ICT
authorswithroles_txt_mv	Saxena, Saurabh @@aut@@
publishDateDaySort_date	2020-06-01T00:00:00Z
hierarchy_top_id	736559264
dewey-sort	14
id	SPR040342395
language_de	englisch
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author	Saxena, Saurabh
spellingShingle	Saxena, Saurabh ddc 004 misc Voltage-mode output driver misc Digital CDR misc Equalization misc Channel loss Wireline communication: the backbone of data transfer
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topic_title	004 ASE Wireline communication: the backbone of data transfer Voltage-mode output driver (dpeaa)DE-He213 Digital CDR (dpeaa)DE-He213 Equalization (dpeaa)DE-He213 Channel loss (dpeaa)DE-He213
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title	Wireline communication: the backbone of data transfer
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title_full	Wireline communication: the backbone of data transfer
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title_sort	wireline communication: the backbone of data transfer
title_auth	Wireline communication: the backbone of data transfer
abstract	Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
abstractGer	Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
abstract_unstemmed	Abstract This paper reviews the need of a high performance wireline communication in the background of wirelessly connected billions of sensor nodes by 2020s. It compares the performance of the state-of-the-art wireline transceivers and underlines the challenges in improving the performance in the midst of tapering in CMOS technology scaling. This paper elaborates on the ongoing research to track the increasing bandwidth requirements in processing platforms with an affordable power budget. Energy efficient design techniques for clock recovery in multilane receivers, receiver frontend in digital CDRs, reconfigurable voltage-mode transmitter, and PAM4 equalizer in full-duplex transceivers are discussed.
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title_short	Wireline communication: the backbone of data transfer
url	https://dx.doi.org/10.1007/s40012-020-00297-1
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up_date	2024-07-03T15:21:49.294Z
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