Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics
Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Roy, Pradip K. [verfasserIn] Laughery, Michael A. [verfasserIn] Chacon, Carlos M. [verfasserIn] Kanan, Ayman M. [verfasserIn] Daugherty, Thomas [verfasserIn] |
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| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1999 |
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| Übergeordnetes Werk: |
Enthalten in: MRS online proceedings library - Warrendale, Pa. : MRS, 1998, 567(1999), 1 vom: Dez., Seite 403-408 |
|---|---|
| Übergeordnetes Werk: |
volume:567 ; year:1999 ; number:1 ; month:12 ; pages:403-408 |
| Links: |
|---|
| DOI / URN: |
10.1557/PROC-567-403 |
|---|
| Katalog-ID: |
SPR041673042 |
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| 520 | |a Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. | ||
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| 700 | 1 | |a Chacon, Carlos M. |e verfasserin |4 aut | |
| 700 | 1 | |a Kanan, Ayman M. |e verfasserin |4 aut | |
| 700 | 1 | |a Daugherty, Thomas |e verfasserin |4 aut | |
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10.1557/PROC-567-403 doi (DE-627)SPR041673042 (SPR)PROC-567-403-e DE-627 ger DE-627 rakwb eng 670 ASE Roy, Pradip K. verfasserin aut Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. Laughery, Michael A. verfasserin aut Chacon, Carlos M. verfasserin aut Kanan, Ayman M. verfasserin aut Daugherty, Thomas verfasserin aut Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 567(1999), 1 vom: Dez., Seite 403-408 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:567 year:1999 number:1 month:12 pages:403-408 https://dx.doi.org/10.1557/PROC-567-403 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 567 1999 1 12 403-408 |
| spelling |
10.1557/PROC-567-403 doi (DE-627)SPR041673042 (SPR)PROC-567-403-e DE-627 ger DE-627 rakwb eng 670 ASE Roy, Pradip K. verfasserin aut Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. Laughery, Michael A. verfasserin aut Chacon, Carlos M. verfasserin aut Kanan, Ayman M. verfasserin aut Daugherty, Thomas verfasserin aut Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 567(1999), 1 vom: Dez., Seite 403-408 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:567 year:1999 number:1 month:12 pages:403-408 https://dx.doi.org/10.1557/PROC-567-403 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 567 1999 1 12 403-408 |
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10.1557/PROC-567-403 doi (DE-627)SPR041673042 (SPR)PROC-567-403-e DE-627 ger DE-627 rakwb eng 670 ASE Roy, Pradip K. verfasserin aut Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. Laughery, Michael A. verfasserin aut Chacon, Carlos M. verfasserin aut Kanan, Ayman M. verfasserin aut Daugherty, Thomas verfasserin aut Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 567(1999), 1 vom: Dez., Seite 403-408 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:567 year:1999 number:1 month:12 pages:403-408 https://dx.doi.org/10.1557/PROC-567-403 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 567 1999 1 12 403-408 |
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10.1557/PROC-567-403 doi (DE-627)SPR041673042 (SPR)PROC-567-403-e DE-627 ger DE-627 rakwb eng 670 ASE Roy, Pradip K. verfasserin aut Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. Laughery, Michael A. verfasserin aut Chacon, Carlos M. verfasserin aut Kanan, Ayman M. verfasserin aut Daugherty, Thomas verfasserin aut Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 567(1999), 1 vom: Dez., Seite 403-408 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:567 year:1999 number:1 month:12 pages:403-408 https://dx.doi.org/10.1557/PROC-567-403 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 567 1999 1 12 403-408 |
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10.1557/PROC-567-403 doi (DE-627)SPR041673042 (SPR)PROC-567-403-e DE-627 ger DE-627 rakwb eng 670 ASE Roy, Pradip K. verfasserin aut Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics 1999 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. Laughery, Michael A. verfasserin aut Chacon, Carlos M. verfasserin aut Kanan, Ayman M. verfasserin aut Daugherty, Thomas verfasserin aut Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 567(1999), 1 vom: Dez., Seite 403-408 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:567 year:1999 number:1 month:12 pages:403-408 https://dx.doi.org/10.1557/PROC-567-403 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 567 1999 1 12 403-408 |
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High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. 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Roy, Pradip K. ddc 670 Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics |
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670 ASE Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics |
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Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics |
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Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics |
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Roy, Pradip K. Laughery, Michael A. Chacon, Carlos M. Kanan, Ayman M. Daugherty, Thomas |
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characterization of the seed $ sio_{2} $ layer in stacked $ sio_{2} $−$ ta_{2} %$ o_{5} $ gate dielectrics |
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Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics |
| abstract |
Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. |
| abstractGer |
Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. |
| abstract_unstemmed |
Abstract A major hurdle in the gate dielectric scaling using conventionally grown $ SiO_{2} $ has been excessive tunneling that occurs in ultra-thin (<25Å) $ SiO_{2} $. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-$ Ta_{2} %$ O_{5} $ interface trap states, and low Silicon interface carrier mobilities. Stacked $ Ta_{2} %$ O_{5} $ gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first $ SiO_{2} $ (8-12Å) layer of the $ SiO_{2} $-$ Ta_{2} %$ O_{5} $ stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness ($ T_{ox} $) of these oxides measured by COS indicates this hydrocarbon layer has no impact on $ T_{ox} $. Stacked $ Ta_{2} %$ O_{5} $ was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick $ Ta_{2} %$ O_{5} $ layer at 480°C, 300mTorr followed by an in-situ 550°C UV-$ 0_{3} $ anneal to densify the $ Ta_{2} %$ O_{5} $ film and grow an additional 5Å $ SiO_{2} $ layer underneath the first grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown $ SiO_{2} $ layer resulting in an effective $ SiO_{2} $ thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements. |
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Characterization of the Seed $ SiO_{2} $ Layer in Stacked $ SiO_{2} $−$ Ta_{2} %$ O_{5} $ Gate Dielectrics |
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