Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics
Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as subs...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Hawkins, William G. [verfasserIn] |
|---|
| Format: |
E-Artikel |
|---|---|
| Sprache: |
Englisch |
| Erschienen: |
1985 |
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| Übergeordnetes Werk: |
Enthalten in: MRS online proceedings library - Warrendale, Pa. : MRS, 1998, 53(1985), 1 vom: 01. Mai, Seite 429-434 |
|---|---|
| Übergeordnetes Werk: |
volume:53 ; year:1985 ; number:1 ; day:01 ; month:05 ; pages:429-434 |
| Links: |
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| DOI / URN: |
10.1557/PROC-53-429 |
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SPR042068061 |
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| 520 | |a Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. | ||
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10.1557/PROC-53-429 doi (DE-627)SPR042068061 (SPR)PROC-53-429-e DE-627 ger DE-627 rakwb eng 670 ASE Hawkins, William G. verfasserin aut Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics 1985 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 53(1985), 1 vom: 01. Mai, Seite 429-434 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:53 year:1985 number:1 day:01 month:05 pages:429-434 https://dx.doi.org/10.1557/PROC-53-429 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 53 1985 1 01 05 429-434 |
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10.1557/PROC-53-429 doi (DE-627)SPR042068061 (SPR)PROC-53-429-e DE-627 ger DE-627 rakwb eng 670 ASE Hawkins, William G. verfasserin aut Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics 1985 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 53(1985), 1 vom: 01. Mai, Seite 429-434 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:53 year:1985 number:1 day:01 month:05 pages:429-434 https://dx.doi.org/10.1557/PROC-53-429 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 53 1985 1 01 05 429-434 |
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10.1557/PROC-53-429 doi (DE-627)SPR042068061 (SPR)PROC-53-429-e DE-627 ger DE-627 rakwb eng 670 ASE Hawkins, William G. verfasserin aut Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics 1985 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 53(1985), 1 vom: 01. Mai, Seite 429-434 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:53 year:1985 number:1 day:01 month:05 pages:429-434 https://dx.doi.org/10.1557/PROC-53-429 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 53 1985 1 01 05 429-434 |
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10.1557/PROC-53-429 doi (DE-627)SPR042068061 (SPR)PROC-53-429-e DE-627 ger DE-627 rakwb eng 670 ASE Hawkins, William G. verfasserin aut Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics 1985 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 53(1985), 1 vom: 01. Mai, Seite 429-434 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:53 year:1985 number:1 day:01 month:05 pages:429-434 https://dx.doi.org/10.1557/PROC-53-429 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 53 1985 1 01 05 429-434 |
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10.1557/PROC-53-429 doi (DE-627)SPR042068061 (SPR)PROC-53-429-e DE-627 ger DE-627 rakwb eng 670 ASE Hawkins, William G. verfasserin aut Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics 1985 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. Enthalten in MRS online proceedings library Warrendale, Pa. : MRS, 1998 53(1985), 1 vom: 01. Mai, Seite 429-434 (DE-627)57782046X (DE-600)2451008-7 1946-4274 nnns volume:53 year:1985 number:1 day:01 month:05 pages:429-434 https://dx.doi.org/10.1557/PROC-53-429 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_2005 AR 53 1985 1 01 05 429-434 |
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| abstract |
Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. |
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Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. |
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Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated. |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR042068061</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20220112051407.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">201126s1985 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1557/PROC-53-429</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR042068061</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)PROC-53-429-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2="4"><subfield code="a">670</subfield><subfield code="q">ASE</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Hawkins, William G.</subfield><subfield code="e">verfasserin</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Low Temperature Polycrystalline Silicon Thin Film Devices for Large Area Electronics</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">1985</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract A process sequence for polycrystalline silicon NMOS logic circuitry is presented here. The fabrication sequence eliminates ion implantation steps and requires a maximum process temperature of 900°C. Low process temperature and diffusion doping may allow use of high temperature glass as substrates. Diffusion doping of large substrates eliminates expensive modification of an ion implanter. Initial work utilized ion implantation to dope device channels before oxidation. Phosphorus channel doping is effective in the control of device threshold, based on the observation that both enhancement and depletion mode device behavior can be obtained. Boron doping is not effective because segregation of the boron into $ SiO_{2} $ occurs during subsequent oxidation. The results obtained from ion implantation doping show that functioning NMOS gates can be fabricated. In fact, it was discovered that undoped polycrystalline silicon channels provide suitable enhancement mode devices, while lightly phosphorus doped channels yield depletion mode devices. A process sequence based solely on phosphorus diffusion is then demonstrated.</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">MRS online proceedings library</subfield><subfield code="d">Warrendale, Pa. : MRS, 1998</subfield><subfield code="g">53(1985), 1 vom: 01. Mai, Seite 429-434</subfield><subfield code="w">(DE-627)57782046X</subfield><subfield code="w">(DE-600)2451008-7</subfield><subfield code="x">1946-4274</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:53</subfield><subfield code="g">year:1985</subfield><subfield code="g">number:1</subfield><subfield code="g">day:01</subfield><subfield code="g">month:05</subfield><subfield code="g">pages:429-434</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1557/PROC-53-429</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">53</subfield><subfield code="j">1985</subfield><subfield code="e">1</subfield><subfield code="b">01</subfield><subfield code="c">05</subfield><subfield code="h">429-434</subfield></datafield></record></collection>
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7.4004126 |