A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS
Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Campos, Arthur Lombardi [verfasserIn] Navarro, João [verfasserIn] Luppe, Maximiliam [verfasserIn] de Lima, Eduardo Rodrigues [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2021 |
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| Schlagwörter: |
Analog-to-digital converter (ADC) |
|---|
| Übergeordnetes Werk: |
Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 106(2021), 1 vom: Jan., Seite 321-337 |
|---|---|
| Übergeordnetes Werk: |
volume:106 ; year:2021 ; number:1 ; month:01 ; pages:321-337 |
| Links: |
|---|
| DOI / URN: |
10.1007/s10470-020-01742-6 |
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| Katalog-ID: |
SPR042961173 |
|---|
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| 100 | 1 | |a Campos, Arthur Lombardi |e verfasserin |4 aut | |
| 245 | 1 | 2 | |a A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS |
| 264 | 1 | |c 2021 | |
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| 520 | |a Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. | ||
| 650 | 4 | |a Analog-to-digital converter (ADC) |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Successive approximation register (SAR) |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Low power consumption |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Asynchronous SAR ADC |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Navarro, João |e verfasserin |4 aut | |
| 700 | 1 | |a Luppe, Maximiliam |e verfasserin |4 aut | |
| 700 | 1 | |a de Lima, Eduardo Rodrigues |e verfasserin |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Analog integrated circuits and signal processing |d Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 |g 106(2021), 1 vom: Jan., Seite 321-337 |w (DE-627)271348925 |w (DE-600)1479772-0 |x 1573-1979 |7 nnns |
| 773 | 1 | 8 | |g volume:106 |g year:2021 |g number:1 |g month:01 |g pages:321-337 |
| 856 | 4 | 0 | |u https://dx.doi.org/10.1007/s10470-020-01742-6 |z kostenfrei |3 Volltext |
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10.1007/s10470-020-01742-6 doi (DE-627)SPR042961173 (DE-599)SPRs10470-020-01742-6-e (SPR)s10470-020-01742-6-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Campos, Arthur Lombardi verfasserin aut A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. Analog-to-digital converter (ADC) (dpeaa)DE-He213 Successive approximation register (SAR) (dpeaa)DE-He213 Low power consumption (dpeaa)DE-He213 Asynchronous SAR ADC (dpeaa)DE-He213 Navarro, João verfasserin aut Luppe, Maximiliam verfasserin aut de Lima, Eduardo Rodrigues verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 106(2021), 1 vom: Jan., Seite 321-337 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:106 year:2021 number:1 month:01 pages:321-337 https://dx.doi.org/10.1007/s10470-020-01742-6 kostenfrei Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 106 2021 1 01 321-337 |
| spelling |
10.1007/s10470-020-01742-6 doi (DE-627)SPR042961173 (DE-599)SPRs10470-020-01742-6-e (SPR)s10470-020-01742-6-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Campos, Arthur Lombardi verfasserin aut A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. Analog-to-digital converter (ADC) (dpeaa)DE-He213 Successive approximation register (SAR) (dpeaa)DE-He213 Low power consumption (dpeaa)DE-He213 Asynchronous SAR ADC (dpeaa)DE-He213 Navarro, João verfasserin aut Luppe, Maximiliam verfasserin aut de Lima, Eduardo Rodrigues verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 106(2021), 1 vom: Jan., Seite 321-337 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:106 year:2021 number:1 month:01 pages:321-337 https://dx.doi.org/10.1007/s10470-020-01742-6 kostenfrei Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 106 2021 1 01 321-337 |
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10.1007/s10470-020-01742-6 doi (DE-627)SPR042961173 (DE-599)SPRs10470-020-01742-6-e (SPR)s10470-020-01742-6-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Campos, Arthur Lombardi verfasserin aut A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. Analog-to-digital converter (ADC) (dpeaa)DE-He213 Successive approximation register (SAR) (dpeaa)DE-He213 Low power consumption (dpeaa)DE-He213 Asynchronous SAR ADC (dpeaa)DE-He213 Navarro, João verfasserin aut Luppe, Maximiliam verfasserin aut de Lima, Eduardo Rodrigues verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 106(2021), 1 vom: Jan., Seite 321-337 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:106 year:2021 number:1 month:01 pages:321-337 https://dx.doi.org/10.1007/s10470-020-01742-6 kostenfrei Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 106 2021 1 01 321-337 |
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10.1007/s10470-020-01742-6 doi (DE-627)SPR042961173 (DE-599)SPRs10470-020-01742-6-e (SPR)s10470-020-01742-6-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Campos, Arthur Lombardi verfasserin aut A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. Analog-to-digital converter (ADC) (dpeaa)DE-He213 Successive approximation register (SAR) (dpeaa)DE-He213 Low power consumption (dpeaa)DE-He213 Asynchronous SAR ADC (dpeaa)DE-He213 Navarro, João verfasserin aut Luppe, Maximiliam verfasserin aut de Lima, Eduardo Rodrigues verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 106(2021), 1 vom: Jan., Seite 321-337 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:106 year:2021 number:1 month:01 pages:321-337 https://dx.doi.org/10.1007/s10470-020-01742-6 kostenfrei Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 106 2021 1 01 321-337 |
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10.1007/s10470-020-01742-6 doi (DE-627)SPR042961173 (DE-599)SPRs10470-020-01742-6-e (SPR)s10470-020-01742-6-e DE-627 ger DE-627 rakwb eng 004 ASE 53.55 bkl 53.73 bkl Campos, Arthur Lombardi verfasserin aut A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. Analog-to-digital converter (ADC) (dpeaa)DE-He213 Successive approximation register (SAR) (dpeaa)DE-He213 Low power consumption (dpeaa)DE-He213 Asynchronous SAR ADC (dpeaa)DE-He213 Navarro, João verfasserin aut Luppe, Maximiliam verfasserin aut de Lima, Eduardo Rodrigues verfasserin aut Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 106(2021), 1 vom: Jan., Seite 321-337 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:106 year:2021 number:1 month:01 pages:321-337 https://dx.doi.org/10.1007/s10470-020-01742-6 kostenfrei Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 53.55 ASE 53.73 ASE AR 106 2021 1 01 321-337 |
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Enthalten in Analog integrated circuits and signal processing 106(2021), 1 vom: Jan., Seite 321-337 volume:106 year:2021 number:1 month:01 pages:321-337 |
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Enthalten in Analog integrated circuits and signal processing 106(2021), 1 vom: Jan., Seite 321-337 volume:106 year:2021 number:1 month:01 pages:321-337 |
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Analog-to-digital converter (ADC) Successive approximation register (SAR) Low power consumption Asynchronous SAR ADC |
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Analog integrated circuits and signal processing |
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Campos, Arthur Lombardi @@aut@@ Navarro, João @@aut@@ Luppe, Maximiliam @@aut@@ de Lima, Eduardo Rodrigues @@aut@@ |
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The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. 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Campos, Arthur Lombardi |
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Campos, Arthur Lombardi ddc 004 bkl 53.55 bkl 53.73 misc Analog-to-digital converter (ADC) misc Successive approximation register (SAR) misc Low power consumption misc Asynchronous SAR ADC A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS |
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004 ASE 53.55 bkl 53.73 bkl A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS Analog-to-digital converter (ADC) (dpeaa)DE-He213 Successive approximation register (SAR) (dpeaa)DE-He213 Low power consumption (dpeaa)DE-He213 Asynchronous SAR ADC (dpeaa)DE-He213 |
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ddc 004 bkl 53.55 bkl 53.73 misc Analog-to-digital converter (ADC) misc Successive approximation register (SAR) misc Low power consumption misc Asynchronous SAR ADC |
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ddc 004 bkl 53.55 bkl 53.73 misc Analog-to-digital converter (ADC) misc Successive approximation register (SAR) misc Low power consumption misc Asynchronous SAR ADC |
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A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS |
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A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS |
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Campos, Arthur Lombardi |
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Analog integrated circuits and signal processing |
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Campos, Arthur Lombardi Navarro, João Luppe, Maximiliam de Lima, Eduardo Rodrigues |
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low-power 10-bit 0.01-to-12-ms/s asynchronous sar adc in 65-nm cmos |
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A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS |
| abstract |
Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. |
| abstractGer |
Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. |
| abstract_unstemmed |
Abstract During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design and implementation of a low power, differential, asynchronous successive approximation register analog-to-digital converter (SAR ADC) in a 65-nm CMOS technology. The ADC works in a flexible range of sampling rates, from a few kS/s up to 12.0 MS/s, being suitable for application in a wide spectrum of low power systems and subsystems, such as biosignal recorder interfaces and frontend of wireless receivers. At maximum sampling rate, the post-layout simulated circuit achieved an effective number of bits (ENOB) of 9.65 and a power consumption of 151.4 µW, leading to a Figure of Merit of 15.8 fJ/Conversion-step; at 10.0 kS/s sampling rate, the ENOB is almost the same, 9.63, but the power consumption is reduced to only 0.26 µW. The occupied area of the implemented ADC is 0.074 $ mm^{2} $. |
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| container_issue |
1 |
| title_short |
A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS |
| url |
https://dx.doi.org/10.1007/s10470-020-01742-6 |
| remote_bool |
true |
| author2 |
Navarro, João Luppe, Maximiliam de Lima, Eduardo Rodrigues |
| author2Str |
Navarro, João Luppe, Maximiliam de Lima, Eduardo Rodrigues |
| ppnlink |
271348925 |
| mediatype_str_mv |
c |
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true |
| hochschulschrift_bool |
false |
| doi_str |
10.1007/s10470-020-01742-6 |
| up_date |
2024-07-03T15:50:18.038Z |
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1803573597873111040 |
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| score |
7.402648 |