A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept

Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS...
Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Kumar, Manoj [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2021

Schlagwörter:	Delay stage Digital phase-locked loop (DPLL) Frequency tuning MOS varactor Phase noise Power consumption

Anmerkung:	© The Institution of Engineers (India) 2021

Übergeordnetes Werk:	Enthalten in: Journal of the Institution of Engineers (India) - [New Delhi] : Springer India, 2012, 103(2021), 1 vom: 05. Juni, Seite 1-11
Übergeordnetes Werk:	volume:103 ; year:2021 ; number:1 ; day:05 ; month:06 ; pages:1-11

Links:	Volltext

DOI / URN:	10.1007/s40031-021-00621-6

Katalog-ID:	SPR046020071

Internformat


LEADER	01000caa a22002652 4500
001	SPR046020071
003	DE-627
005	20230507085417.0
007	cr uuu---uuuuu
008	220121s2021 xx \|\|\|\|\|o 00\| \|\|eng c
024	7		\|a 10.1007/s40031-021-00621-6 \|2 doi
035			\|a (DE-627)SPR046020071
035			\|a (SPR)s40031-021-00621-6-e
040			\|a DE-627 \|b ger \|c DE-627 \|e rakwb
041			\|a eng
100	1		\|a Kumar, Manoj \|e verfasserin \|0 (orcid)0000-0002-1863-4189 \|4 aut
245	1	2	\|a A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept
264		1	\|c 2021
336			\|a Text \|b txt \|2 rdacontent
337			\|a Computermedien \|b c \|2 rdamedia
338			\|a Online-Ressource \|b cr \|2 rdacarrier
500			\|a © The Institution of Engineers (India) 2021
520			\|a Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.
650		4	\|a Delay stage \|7 (dpeaa)DE-He213
650		4	\|a Digital phase-locked loop (DPLL) \|7 (dpeaa)DE-He213
650		4	\|a Frequency tuning \|7 (dpeaa)DE-He213
650		4	\|a MOS varactor \|7 (dpeaa)DE-He213
650		4	\|a Phase noise \|7 (dpeaa)DE-He213
650		4	\|a Power consumption \|7 (dpeaa)DE-He213
773	0	8	\|i Enthalten in \|t Journal of the Institution of Engineers (India) \|d [New Delhi] : Springer India, 2012 \|g 103(2021), 1 vom: 05. Juni, Seite 1-11 \|w (DE-627)722236980 \|w (DE-600)2677588-8 \|x 2250-2114 \|7 nnns
773	1	8	\|g volume:103 \|g year:2021 \|g number:1 \|g day:05 \|g month:06 \|g pages:1-11
856	4	0	\|u https://dx.doi.org/10.1007/s40031-021-00621-6 \|z lizenzpflichtig \|3 Volltext
912			\|a GBV_USEFLAG_A
912			\|a SYSFLAG_A
912			\|a GBV_SPRINGER
912			\|a GBV_ILN_11
912			\|a GBV_ILN_20
912			\|a GBV_ILN_22
912			\|a GBV_ILN_23
912			\|a GBV_ILN_24
912			\|a GBV_ILN_31
912			\|a GBV_ILN_32
912			\|a GBV_ILN_39
912			\|a GBV_ILN_40
912			\|a GBV_ILN_60
912			\|a GBV_ILN_62
912			\|a GBV_ILN_63
912			\|a GBV_ILN_65
912			\|a GBV_ILN_69
912			\|a GBV_ILN_70
912			\|a GBV_ILN_73
912			\|a GBV_ILN_74
912			\|a GBV_ILN_90
912			\|a GBV_ILN_95
912			\|a GBV_ILN_100
912			\|a GBV_ILN_105
912			\|a GBV_ILN_110
912			\|a GBV_ILN_120
912			\|a GBV_ILN_138
912			\|a GBV_ILN_150
912			\|a GBV_ILN_151
912			\|a GBV_ILN_152
912			\|a GBV_ILN_161
912			\|a GBV_ILN_170
912			\|a GBV_ILN_171
912			\|a GBV_ILN_187
912			\|a GBV_ILN_213
912			\|a GBV_ILN_224
912			\|a GBV_ILN_230
912			\|a GBV_ILN_250
912			\|a GBV_ILN_281
912			\|a GBV_ILN_285
912			\|a GBV_ILN_293
912			\|a GBV_ILN_370
912			\|a GBV_ILN_602
912			\|a GBV_ILN_636
912			\|a GBV_ILN_702
912			\|a GBV_ILN_2001
912			\|a GBV_ILN_2003
912			\|a GBV_ILN_2004
912			\|a GBV_ILN_2005
912			\|a GBV_ILN_2006
912			\|a GBV_ILN_2007
912			\|a GBV_ILN_2008
912			\|a GBV_ILN_2009
912			\|a GBV_ILN_2010
912			\|a GBV_ILN_2011
912			\|a GBV_ILN_2014
912			\|a GBV_ILN_2015
912			\|a GBV_ILN_2020
912			\|a GBV_ILN_2021
912			\|a GBV_ILN_2025
912			\|a GBV_ILN_2026
912			\|a GBV_ILN_2027
912			\|a GBV_ILN_2031
912			\|a GBV_ILN_2034
912			\|a GBV_ILN_2037
912			\|a GBV_ILN_2038
912			\|a GBV_ILN_2039
912			\|a GBV_ILN_2044
912			\|a GBV_ILN_2048
912			\|a GBV_ILN_2049
912			\|a GBV_ILN_2050
912			\|a GBV_ILN_2055
912			\|a GBV_ILN_2056
912			\|a GBV_ILN_2057
912			\|a GBV_ILN_2059
912			\|a GBV_ILN_2061
912			\|a GBV_ILN_2064
912			\|a GBV_ILN_2065
912			\|a GBV_ILN_2068
912			\|a GBV_ILN_2088
912			\|a GBV_ILN_2093
912			\|a GBV_ILN_2106
912			\|a GBV_ILN_2107
912			\|a GBV_ILN_2108
912			\|a GBV_ILN_2110
912			\|a GBV_ILN_2111
912			\|a GBV_ILN_2112
912			\|a GBV_ILN_2113
912			\|a GBV_ILN_2118
912			\|a GBV_ILN_2122
912			\|a GBV_ILN_2129
912			\|a GBV_ILN_2143
912			\|a GBV_ILN_2144
912			\|a GBV_ILN_2147
912			\|a GBV_ILN_2148
912			\|a GBV_ILN_2152
912			\|a GBV_ILN_2153
912			\|a GBV_ILN_2188
912			\|a GBV_ILN_2232
912			\|a GBV_ILN_2336
912			\|a GBV_ILN_2446
912			\|a GBV_ILN_2470
912			\|a GBV_ILN_2472
912			\|a GBV_ILN_2507
912			\|a GBV_ILN_2522
912			\|a GBV_ILN_2548
912			\|a GBV_ILN_4035
912			\|a GBV_ILN_4037
912			\|a GBV_ILN_4046
912			\|a GBV_ILN_4112
912			\|a GBV_ILN_4125
912			\|a GBV_ILN_4126
912			\|a GBV_ILN_4242
912			\|a GBV_ILN_4246
912			\|a GBV_ILN_4249
912			\|a GBV_ILN_4251
912			\|a GBV_ILN_4305
912			\|a GBV_ILN_4306
912			\|a GBV_ILN_4307
912			\|a GBV_ILN_4313
912			\|a GBV_ILN_4322
912			\|a GBV_ILN_4323
912			\|a GBV_ILN_4324
912			\|a GBV_ILN_4325
912			\|a GBV_ILN_4326
912			\|a GBV_ILN_4328
912			\|a GBV_ILN_4333
912			\|a GBV_ILN_4334
912			\|a GBV_ILN_4335
912			\|a GBV_ILN_4336
912			\|a GBV_ILN_4338
912			\|a GBV_ILN_4393
912			\|a GBV_ILN_4700
951			\|a AR
952			\|d 103 \|j 2021 \|e 1 \|b 05 \|c 06 \|h 1-11

Indexfelder

author_variant	m k mk
matchkey_str	article:22502114:2021----::lwoedgtlyotoldigsiltreinihms
hierarchy_sort_str	2021
publishDate	2021
allfields	10.1007/s40031-021-00621-6 doi (DE-627)SPR046020071 (SPR)s40031-021-00621-6-e DE-627 ger DE-627 rakwb eng Kumar, Manoj verfasserin (orcid)0000-0002-1863-4189 aut A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Institution of Engineers (India) 2021 Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. Delay stage (dpeaa)DE-He213 Digital phase-locked loop (DPLL) (dpeaa)DE-He213 Frequency tuning (dpeaa)DE-He213 MOS varactor (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Enthalten in Journal of the Institution of Engineers (India) [New Delhi] : Springer India, 2012 103(2021), 1 vom: 05. Juni, Seite 1-11 (DE-627)722236980 (DE-600)2677588-8 2250-2114 nnns volume:103 year:2021 number:1 day:05 month:06 pages:1-11 https://dx.doi.org/10.1007/s40031-021-00621-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 103 2021 1 05 06 1-11
spelling	10.1007/s40031-021-00621-6 doi (DE-627)SPR046020071 (SPR)s40031-021-00621-6-e DE-627 ger DE-627 rakwb eng Kumar, Manoj verfasserin (orcid)0000-0002-1863-4189 aut A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Institution of Engineers (India) 2021 Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. Delay stage (dpeaa)DE-He213 Digital phase-locked loop (DPLL) (dpeaa)DE-He213 Frequency tuning (dpeaa)DE-He213 MOS varactor (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Enthalten in Journal of the Institution of Engineers (India) [New Delhi] : Springer India, 2012 103(2021), 1 vom: 05. Juni, Seite 1-11 (DE-627)722236980 (DE-600)2677588-8 2250-2114 nnns volume:103 year:2021 number:1 day:05 month:06 pages:1-11 https://dx.doi.org/10.1007/s40031-021-00621-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 103 2021 1 05 06 1-11
allfields_unstemmed	10.1007/s40031-021-00621-6 doi (DE-627)SPR046020071 (SPR)s40031-021-00621-6-e DE-627 ger DE-627 rakwb eng Kumar, Manoj verfasserin (orcid)0000-0002-1863-4189 aut A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Institution of Engineers (India) 2021 Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. Delay stage (dpeaa)DE-He213 Digital phase-locked loop (DPLL) (dpeaa)DE-He213 Frequency tuning (dpeaa)DE-He213 MOS varactor (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Enthalten in Journal of the Institution of Engineers (India) [New Delhi] : Springer India, 2012 103(2021), 1 vom: 05. Juni, Seite 1-11 (DE-627)722236980 (DE-600)2677588-8 2250-2114 nnns volume:103 year:2021 number:1 day:05 month:06 pages:1-11 https://dx.doi.org/10.1007/s40031-021-00621-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 103 2021 1 05 06 1-11
allfieldsGer	10.1007/s40031-021-00621-6 doi (DE-627)SPR046020071 (SPR)s40031-021-00621-6-e DE-627 ger DE-627 rakwb eng Kumar, Manoj verfasserin (orcid)0000-0002-1863-4189 aut A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Institution of Engineers (India) 2021 Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. Delay stage (dpeaa)DE-He213 Digital phase-locked loop (DPLL) (dpeaa)DE-He213 Frequency tuning (dpeaa)DE-He213 MOS varactor (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Enthalten in Journal of the Institution of Engineers (India) [New Delhi] : Springer India, 2012 103(2021), 1 vom: 05. Juni, Seite 1-11 (DE-627)722236980 (DE-600)2677588-8 2250-2114 nnns volume:103 year:2021 number:1 day:05 month:06 pages:1-11 https://dx.doi.org/10.1007/s40031-021-00621-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 103 2021 1 05 06 1-11
allfieldsSound	10.1007/s40031-021-00621-6 doi (DE-627)SPR046020071 (SPR)s40031-021-00621-6-e DE-627 ger DE-627 rakwb eng Kumar, Manoj verfasserin (orcid)0000-0002-1863-4189 aut A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Institution of Engineers (India) 2021 Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. Delay stage (dpeaa)DE-He213 Digital phase-locked loop (DPLL) (dpeaa)DE-He213 Frequency tuning (dpeaa)DE-He213 MOS varactor (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213 Enthalten in Journal of the Institution of Engineers (India) [New Delhi] : Springer India, 2012 103(2021), 1 vom: 05. Juni, Seite 1-11 (DE-627)722236980 (DE-600)2677588-8 2250-2114 nnns volume:103 year:2021 number:1 day:05 month:06 pages:1-11 https://dx.doi.org/10.1007/s40031-021-00621-6 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 103 2021 1 05 06 1-11
language	English
source	Enthalten in Journal of the Institution of Engineers (India) 103(2021), 1 vom: 05. Juni, Seite 1-11 volume:103 year:2021 number:1 day:05 month:06 pages:1-11
sourceStr	Enthalten in Journal of the Institution of Engineers (India) 103(2021), 1 vom: 05. Juni, Seite 1-11 volume:103 year:2021 number:1 day:05 month:06 pages:1-11
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	Delay stage Digital phase-locked loop (DPLL) Frequency tuning MOS varactor Phase noise Power consumption
isfreeaccess_bool	false
container_title	Journal of the Institution of Engineers (India)
authorswithroles_txt_mv	Kumar, Manoj @@aut@@
publishDateDaySort_date	2021-06-05T00:00:00Z
hierarchy_top_id	722236980
id	SPR046020071
language_de	englisch
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR046020071</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230507085417.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220121s2021 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s40031-021-00621-6</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR046020071</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s40031-021-00621-6-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kumar, Manoj</subfield><subfield code="e">verfasserin</subfield><subfield code="0">(orcid)0000-0002-1863-4189</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2021</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© The Institution of Engineers (India) 2021</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delay stage</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digital phase-locked loop (DPLL)</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Frequency tuning</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">MOS varactor</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power consumption</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of the Institution of Engineers (India)</subfield><subfield code="d">[New Delhi] : Springer India, 2012</subfield><subfield code="g">103(2021), 1 vom: 05. Juni, Seite 1-11</subfield><subfield code="w">(DE-627)722236980</subfield><subfield code="w">(DE-600)2677588-8</subfield><subfield code="x">2250-2114</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:103</subfield><subfield code="g">year:2021</subfield><subfield code="g">number:1</subfield><subfield code="g">day:05</subfield><subfield code="g">month:06</subfield><subfield code="g">pages:1-11</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s40031-021-00621-6</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_31</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_32</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_74</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_90</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_100</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_120</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_138</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_150</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_171</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_187</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_224</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_250</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_281</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_636</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_702</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2001</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2003</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2007</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2008</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2009</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2010</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2011</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2015</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2020</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2021</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2025</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2026</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2031</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2034</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2038</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2039</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2044</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2048</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2049</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2050</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2055</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2056</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2057</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2059</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2064</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2065</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2068</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2088</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2093</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2106</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2107</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2108</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2111</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2113</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2118</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2122</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2129</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2143</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2144</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2147</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2148</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2153</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2188</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2232</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2446</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2470</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2472</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2507</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2522</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2548</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4035</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4046</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4242</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4246</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4251</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4326</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4328</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4333</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4334</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4393</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">103</subfield><subfield code="j">2021</subfield><subfield code="e">1</subfield><subfield code="b">05</subfield><subfield code="c">06</subfield><subfield code="h">1-11</subfield></datafield></record></collection>
author	Kumar, Manoj
spellingShingle	Kumar, Manoj misc Delay stage misc Digital phase-locked loop (DPLL) misc Frequency tuning misc MOS varactor misc Phase noise misc Power consumption A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept
authorStr	Kumar, Manoj
ppnlink_with_tag_str_mv	@@773@@(DE-627)722236980
format	electronic Article
delete_txt_mv	keep
author_role	aut
collection	springer
remote_str	true
illustrated	Not Illustrated
issn	2250-2114
topic_title	A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept Delay stage (dpeaa)DE-He213 Digital phase-locked loop (DPLL) (dpeaa)DE-He213 Frequency tuning (dpeaa)DE-He213 MOS varactor (dpeaa)DE-He213 Phase noise (dpeaa)DE-He213 Power consumption (dpeaa)DE-He213
topic	misc Delay stage misc Digital phase-locked loop (DPLL) misc Frequency tuning misc MOS varactor misc Phase noise misc Power consumption
topic_unstemmed	misc Delay stage misc Digital phase-locked loop (DPLL) misc Frequency tuning misc MOS varactor misc Phase noise misc Power consumption
topic_browse	misc Delay stage misc Digital phase-locked loop (DPLL) misc Frequency tuning misc MOS varactor misc Phase noise misc Power consumption
format_facet	Elektronische Aufsätze Aufsätze Elektronische Ressource
format_main_str_mv	Text Zeitschrift/Artikel
carriertype_str_mv	cr
hierarchy_parent_title	Journal of the Institution of Engineers (India)
hierarchy_parent_id	722236980
hierarchy_top_title	Journal of the Institution of Engineers (India)
isfreeaccess_txt	false
familylinks_str_mv	(DE-627)722236980 (DE-600)2677588-8
title	A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept
ctrlnum	(DE-627)SPR046020071 (SPR)s40031-021-00621-6-e
title_full	A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept
author_sort	Kumar, Manoj
journal	Journal of the Institution of Engineers (India)
journalStr	Journal of the Institution of Engineers (India)
lang_code	eng
isOA_bool	false
recordtype	marc
publishDateSort	2021
contenttype_str_mv	txt
container_start_page	1
author_browse	Kumar, Manoj
container_volume	103
format_se	Elektronische Aufsätze
author-letter	Kumar, Manoj
doi_str_mv	10.1007/s40031-021-00621-6
normlink	(ORCID)0000-0002-1863-4189
normlink_prefix_str_mv	(orcid)0000-0002-1863-4189
title_sort	low-power digitally controlled ring oscillator design with imos varactor tuning concept
title_auth	A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept
abstract	Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. © The Institution of Engineers (India) 2021
abstractGer	Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. © The Institution of Engineers (India) 2021
abstract_unstemmed	Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage. © The Institution of Engineers (India) 2021
collection_details	GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700
container_issue	1
title_short	A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept
url	https://dx.doi.org/10.1007/s40031-021-00621-6
remote_bool	true
ppnlink	722236980
mediatype_str_mv	c
isOA_txt	false
hochschulschrift_bool	false
doi_str	10.1007/s40031-021-00621-6
up_date	2024-07-03T19:48:51.959Z
_version_	1803588607111331840
fullrecord_marcxml	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR046020071</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230507085417.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220121s2021 xx \|\|\|\|\|o 00\| \|\|eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s40031-021-00621-6</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR046020071</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s40031-021-00621-6-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Kumar, Manoj</subfield><subfield code="e">verfasserin</subfield><subfield code="0">(orcid)0000-0002-1863-4189</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2021</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© The Institution of Engineers (India) 2021</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.9051 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Delay stage</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Digital phase-locked loop (DPLL)</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Frequency tuning</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">MOS varactor</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Phase noise</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Power consumption</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Journal of the Institution of Engineers (India)</subfield><subfield code="d">[New Delhi] : Springer India, 2012</subfield><subfield code="g">103(2021), 1 vom: 05. Juni, Seite 1-11</subfield><subfield code="w">(DE-627)722236980</subfield><subfield code="w">(DE-600)2677588-8</subfield><subfield code="x">2250-2114</subfield><subfield code="7">nnns</subfield></datafield><datafield tag="773" ind1="1" ind2="8"><subfield code="g">volume:103</subfield><subfield code="g">year:2021</subfield><subfield code="g">number:1</subfield><subfield code="g">day:05</subfield><subfield code="g">month:06</subfield><subfield code="g">pages:1-11</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://dx.doi.org/10.1007/s40031-021-00621-6</subfield><subfield code="z">lizenzpflichtig</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_USEFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">SYSFLAG_A</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_SPRINGER</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_11</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_20</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_22</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_23</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_24</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_31</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_32</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_39</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_40</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_60</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_62</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_63</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_65</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_69</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_70</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_73</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_74</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_90</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_95</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_100</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_105</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_120</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_138</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_150</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_151</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_161</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_170</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_171</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_187</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_213</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_224</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_230</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_250</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_281</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_285</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_293</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_370</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_602</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_636</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_702</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2001</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2003</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2004</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2005</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2006</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2007</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2008</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2009</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2010</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2011</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2014</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2015</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2020</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2021</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2025</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2026</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2027</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2031</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2034</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2038</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2039</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2044</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2048</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2049</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2050</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2055</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2056</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2057</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2059</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2061</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2064</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2065</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2068</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2088</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2093</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2106</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2107</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2108</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2110</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2111</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2113</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2118</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2122</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2129</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2143</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2144</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2147</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2148</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2152</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2153</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2188</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2232</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2446</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2470</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2472</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2507</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2522</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_2548</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4035</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4037</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4046</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4112</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4125</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4126</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4242</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4246</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4249</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4251</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4305</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4306</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4307</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4313</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4322</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4323</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4324</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4325</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4326</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4328</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4333</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4334</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4335</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4336</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4338</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4393</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">GBV_ILN_4700</subfield></datafield><datafield tag="951" ind1=" " ind2=" "><subfield code="a">AR</subfield></datafield><datafield tag="952" ind1=" " ind2=" "><subfield code="d">103</subfield><subfield code="j">2021</subfield><subfield code="e">1</subfield><subfield code="b">05</subfield><subfield code="c">06</subfield><subfield code="h">1-11</subfield></datafield></record></collection>
score	7.401457

Nicht das Richtige dabei?

Schreiben Sie uns!

A Low-Power Digitally Controlled Ring Oscillator Design with IMOS Varactor Tuning Concept

Nicht das Richtige dabei?

Zugang & Verfügbarkeit

Vorhandene Bände

Nicht das Richtige dabei?