A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration
Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet s...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Ajabi, Shahrzad [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2021 |
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| Schlagwörter: |
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| Anmerkung: |
© Shiraz University 2021 |
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| Übergeordnetes Werk: |
Enthalten in: Iranian journal of science and technology - Cham, Switzerland : Springer International Publishing, 1999, 46(2021), 1 vom: 28. Juli, Seite 225-234 |
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| Übergeordnetes Werk: |
volume:46 ; year:2021 ; number:1 ; day:28 ; month:07 ; pages:225-234 |
| Links: |
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| DOI / URN: |
10.1007/s40998-021-00450-9 |
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| Katalog-ID: |
SPR04625661X |
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| 100 | 1 | |a Ajabi, Shahrzad |e verfasserin |0 (orcid)0000-0001-7183-991X |4 aut | |
| 245 | 1 | 2 | |a A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration |
| 264 | 1 | |c 2021 | |
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| 500 | |a © Shiraz University 2021 | ||
| 520 | |a Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. | ||
| 650 | 4 | |a Linear |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Low-noise amplifier |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a LNA |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Differential quartet |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Design methodology |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Kaabi, Hooman |4 aut | |
| 773 | 0 | 8 | |i Enthalten in |t Iranian journal of science and technology |d Cham, Switzerland : Springer International Publishing, 1999 |g 46(2021), 1 vom: 28. Juli, Seite 225-234 |w (DE-627)844130222 |w (DE-600)2842937-0 |x 2364-1827 |7 nnns |
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| 952 | |d 46 |j 2021 |e 1 |b 28 |c 07 |h 225-234 | ||
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10.1007/s40998-021-00450-9 doi (DE-627)SPR04625661X (SPR)s40998-021-00450-9-e DE-627 ger DE-627 rakwb eng Ajabi, Shahrzad verfasserin (orcid)0000-0001-7183-991X aut A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Shiraz University 2021 Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. Linear (dpeaa)DE-He213 Low-noise amplifier (dpeaa)DE-He213 LNA (dpeaa)DE-He213 Differential quartet (dpeaa)DE-He213 Design methodology (dpeaa)DE-He213 Kaabi, Hooman aut Enthalten in Iranian journal of science and technology Cham, Switzerland : Springer International Publishing, 1999 46(2021), 1 vom: 28. Juli, Seite 225-234 (DE-627)844130222 (DE-600)2842937-0 2364-1827 nnns volume:46 year:2021 number:1 day:28 month:07 pages:225-234 https://dx.doi.org/10.1007/s40998-021-00450-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_165 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 46 2021 1 28 07 225-234 |
| spelling |
10.1007/s40998-021-00450-9 doi (DE-627)SPR04625661X (SPR)s40998-021-00450-9-e DE-627 ger DE-627 rakwb eng Ajabi, Shahrzad verfasserin (orcid)0000-0001-7183-991X aut A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Shiraz University 2021 Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. Linear (dpeaa)DE-He213 Low-noise amplifier (dpeaa)DE-He213 LNA (dpeaa)DE-He213 Differential quartet (dpeaa)DE-He213 Design methodology (dpeaa)DE-He213 Kaabi, Hooman aut Enthalten in Iranian journal of science and technology Cham, Switzerland : Springer International Publishing, 1999 46(2021), 1 vom: 28. Juli, Seite 225-234 (DE-627)844130222 (DE-600)2842937-0 2364-1827 nnns volume:46 year:2021 number:1 day:28 month:07 pages:225-234 https://dx.doi.org/10.1007/s40998-021-00450-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_165 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 46 2021 1 28 07 225-234 |
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10.1007/s40998-021-00450-9 doi (DE-627)SPR04625661X (SPR)s40998-021-00450-9-e DE-627 ger DE-627 rakwb eng Ajabi, Shahrzad verfasserin (orcid)0000-0001-7183-991X aut A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Shiraz University 2021 Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. Linear (dpeaa)DE-He213 Low-noise amplifier (dpeaa)DE-He213 LNA (dpeaa)DE-He213 Differential quartet (dpeaa)DE-He213 Design methodology (dpeaa)DE-He213 Kaabi, Hooman aut Enthalten in Iranian journal of science and technology Cham, Switzerland : Springer International Publishing, 1999 46(2021), 1 vom: 28. Juli, Seite 225-234 (DE-627)844130222 (DE-600)2842937-0 2364-1827 nnns volume:46 year:2021 number:1 day:28 month:07 pages:225-234 https://dx.doi.org/10.1007/s40998-021-00450-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_165 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 46 2021 1 28 07 225-234 |
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10.1007/s40998-021-00450-9 doi (DE-627)SPR04625661X (SPR)s40998-021-00450-9-e DE-627 ger DE-627 rakwb eng Ajabi, Shahrzad verfasserin (orcid)0000-0001-7183-991X aut A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Shiraz University 2021 Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. Linear (dpeaa)DE-He213 Low-noise amplifier (dpeaa)DE-He213 LNA (dpeaa)DE-He213 Differential quartet (dpeaa)DE-He213 Design methodology (dpeaa)DE-He213 Kaabi, Hooman aut Enthalten in Iranian journal of science and technology Cham, Switzerland : Springer International Publishing, 1999 46(2021), 1 vom: 28. Juli, Seite 225-234 (DE-627)844130222 (DE-600)2842937-0 2364-1827 nnns volume:46 year:2021 number:1 day:28 month:07 pages:225-234 https://dx.doi.org/10.1007/s40998-021-00450-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_165 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 46 2021 1 28 07 225-234 |
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10.1007/s40998-021-00450-9 doi (DE-627)SPR04625661X (SPR)s40998-021-00450-9-e DE-627 ger DE-627 rakwb eng Ajabi, Shahrzad verfasserin (orcid)0000-0001-7183-991X aut A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © Shiraz University 2021 Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. Linear (dpeaa)DE-He213 Low-noise amplifier (dpeaa)DE-He213 LNA (dpeaa)DE-He213 Differential quartet (dpeaa)DE-He213 Design methodology (dpeaa)DE-He213 Kaabi, Hooman aut Enthalten in Iranian journal of science and technology Cham, Switzerland : Springer International Publishing, 1999 46(2021), 1 vom: 28. Juli, Seite 225-234 (DE-627)844130222 (DE-600)2842937-0 2364-1827 nnns volume:46 year:2021 number:1 day:28 month:07 pages:225-234 https://dx.doi.org/10.1007/s40998-021-00450-9 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_165 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 46 2021 1 28 07 225-234 |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR04625661X</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230507110904.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220217s2021 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s40998-021-00450-9</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR04625661X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s40998-021-00450-9-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ajabi, Shahrzad</subfield><subfield code="e">verfasserin</subfield><subfield code="0">(orcid)0000-0001-7183-991X</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2021</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© Shiraz University 2021</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. 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Ajabi, Shahrzad |
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A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration Linear (dpeaa)DE-He213 Low-noise amplifier (dpeaa)DE-He213 LNA (dpeaa)DE-He213 Differential quartet (dpeaa)DE-He213 Design methodology (dpeaa)DE-He213 |
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A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration |
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24ghz high dynamic range low-noise amplifier design optimization methodology and circuit configuration |
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A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration |
| abstract |
Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. © Shiraz University 2021 |
| abstractGer |
Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. © Shiraz University 2021 |
| abstract_unstemmed |
Abstract In addition to low noise figure (NF) and high gain, 1-dB compression point (P1dB) and the input third-order intercept point (IIP3) are critical in the design of a high dynamic range low-noise amplifier (LNA). An improved and optimized highly linear LNA configured by a differential quartet structure is proposed. The differential quartet topology is more linear than the conventional differential topology. The differential trans-conductance of the differential quartet topology is smooth for a wider range of input voltage variations. The equations for the performance parameters of the LNA are extracted. Moreover, a specific step-by-step method is described for this topology. Using this, regular method leads to simultaneous improvements in the specifications of the amplifier. A 24GHz LNA is designed in a standard 180 nm CMOS technology. The layout parasitic effects are extracted using electromagnetic (EM) simulation. The optimized LNA achieves an input/output return loss of %$- 15.6/ - 11.7%$ dB. The simulation results show a peak S21 of 10.27 dB at 23.72 GHz, an NF of 3.3 dB, and a P1dB of − 5 dB at 24 GHz. Furthermore, IIP3 is 11.68 dBm, the power consumption at the 3V supply voltage is 17.8 mW, and the core layout size is 580 μm × 640 μm. © Shiraz University 2021 |
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A 24GHz High Dynamic Range Low-Noise Amplifier Design Optimization Methodology and Circuit Configuration |
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https://dx.doi.org/10.1007/s40998-021-00450-9 |
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Kaabi, Hooman |
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10.1007/s40998-021-00450-9 |
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| score |
7.399583 |