± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower
Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two bia...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Yesil, Abdullah [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2021 |
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| Schlagwörter: |
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| Anmerkung: |
© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 |
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| Übergeordnetes Werk: |
Enthalten in: Circuits, systems and signal processing - Boston, Mass. : Birkhäuser, 1982, 41(2021), 4 vom: 23. Okt., Seite 1819-1833 |
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| Übergeordnetes Werk: |
volume:41 ; year:2021 ; number:4 ; day:23 ; month:10 ; pages:1819-1833 |
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| DOI / URN: |
10.1007/s00034-021-01867-7 |
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| Katalog-ID: |
SPR046359966 |
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| 100 | 1 | |a Yesil, Abdullah |e verfasserin |0 (orcid)0000-0002-0607-8226 |4 aut | |
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| 520 | |a Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. | ||
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| 700 | 1 | |a Minaei, Shahram |4 aut | |
| 700 | 1 | |a Psychalinos, Costas |4 aut | |
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10.1007/s00034-021-01867-7 doi (DE-627)SPR046359966 (SPR)s00034-021-01867-7-e DE-627 ger DE-627 rakwb eng Yesil, Abdullah verfasserin (orcid)0000-0002-0607-8226 aut ± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. VCII (dpeaa)DE-He213 Voltage conveyor (dpeaa)DE-He213 Super source follower (dpeaa)DE-He213 Low voltage (dpeaa)DE-He213 Low power (dpeaa)DE-He213 CMOS analog integrated circuits (dpeaa)DE-He213 Minaei, Shahram aut Psychalinos, Costas aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 41(2021), 4 vom: 23. Okt., Seite 1819-1833 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:41 year:2021 number:4 day:23 month:10 pages:1819-1833 https://dx.doi.org/10.1007/s00034-021-01867-7 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 41 2021 4 23 10 1819-1833 |
| spelling |
10.1007/s00034-021-01867-7 doi (DE-627)SPR046359966 (SPR)s00034-021-01867-7-e DE-627 ger DE-627 rakwb eng Yesil, Abdullah verfasserin (orcid)0000-0002-0607-8226 aut ± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. VCII (dpeaa)DE-He213 Voltage conveyor (dpeaa)DE-He213 Super source follower (dpeaa)DE-He213 Low voltage (dpeaa)DE-He213 Low power (dpeaa)DE-He213 CMOS analog integrated circuits (dpeaa)DE-He213 Minaei, Shahram aut Psychalinos, Costas aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 41(2021), 4 vom: 23. Okt., Seite 1819-1833 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:41 year:2021 number:4 day:23 month:10 pages:1819-1833 https://dx.doi.org/10.1007/s00034-021-01867-7 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 41 2021 4 23 10 1819-1833 |
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10.1007/s00034-021-01867-7 doi (DE-627)SPR046359966 (SPR)s00034-021-01867-7-e DE-627 ger DE-627 rakwb eng Yesil, Abdullah verfasserin (orcid)0000-0002-0607-8226 aut ± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. VCII (dpeaa)DE-He213 Voltage conveyor (dpeaa)DE-He213 Super source follower (dpeaa)DE-He213 Low voltage (dpeaa)DE-He213 Low power (dpeaa)DE-He213 CMOS analog integrated circuits (dpeaa)DE-He213 Minaei, Shahram aut Psychalinos, Costas aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 41(2021), 4 vom: 23. Okt., Seite 1819-1833 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:41 year:2021 number:4 day:23 month:10 pages:1819-1833 https://dx.doi.org/10.1007/s00034-021-01867-7 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 41 2021 4 23 10 1819-1833 |
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10.1007/s00034-021-01867-7 doi (DE-627)SPR046359966 (SPR)s00034-021-01867-7-e DE-627 ger DE-627 rakwb eng Yesil, Abdullah verfasserin (orcid)0000-0002-0607-8226 aut ± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. VCII (dpeaa)DE-He213 Voltage conveyor (dpeaa)DE-He213 Super source follower (dpeaa)DE-He213 Low voltage (dpeaa)DE-He213 Low power (dpeaa)DE-He213 CMOS analog integrated circuits (dpeaa)DE-He213 Minaei, Shahram aut Psychalinos, Costas aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 41(2021), 4 vom: 23. Okt., Seite 1819-1833 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:41 year:2021 number:4 day:23 month:10 pages:1819-1833 https://dx.doi.org/10.1007/s00034-021-01867-7 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 41 2021 4 23 10 1819-1833 |
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10.1007/s00034-021-01867-7 doi (DE-627)SPR046359966 (SPR)s00034-021-01867-7-e DE-627 ger DE-627 rakwb eng Yesil, Abdullah verfasserin (orcid)0000-0002-0607-8226 aut ± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower 2021 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. VCII (dpeaa)DE-He213 Voltage conveyor (dpeaa)DE-He213 Super source follower (dpeaa)DE-He213 Low voltage (dpeaa)DE-He213 Low power (dpeaa)DE-He213 CMOS analog integrated circuits (dpeaa)DE-He213 Minaei, Shahram aut Psychalinos, Costas aut Enthalten in Circuits, systems and signal processing Boston, Mass. : Birkhäuser, 1982 41(2021), 4 vom: 23. Okt., Seite 1819-1833 (DE-627)351975470 (DE-600)2085136-4 1531-5878 nnns volume:41 year:2021 number:4 day:23 month:10 pages:1819-1833 https://dx.doi.org/10.1007/s00034-021-01867-7 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_267 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2119 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 41 2021 4 23 10 1819-1833 |
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Yesil, Abdullah @@aut@@ Minaei, Shahram @@aut@@ Psychalinos, Costas @@aut@@ |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000caa a22002652 4500</leader><controlfield tag="001">SPR046359966</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20230507121355.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">220302s2021 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s00034-021-01867-7</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR046359966</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s00034-021-01867-7-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Yesil, Abdullah</subfield><subfield code="e">verfasserin</subfield><subfield code="0">(orcid)0000-0002-0607-8226</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2021</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. 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Yesil, Abdullah |
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Yesil, Abdullah misc VCII misc Voltage conveyor misc Super source follower misc Low voltage misc Low power misc CMOS analog integrated circuits ± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower |
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± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower VCII (dpeaa)DE-He213 Voltage conveyor (dpeaa)DE-He213 Super source follower (dpeaa)DE-He213 Low voltage (dpeaa)DE-He213 Low power (dpeaa)DE-He213 CMOS analog integrated circuits (dpeaa)DE-He213 |
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± 0.45 v cmos second-generation voltage conveyor based on super source follower |
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± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower |
| abstract |
Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 |
| abstractGer |
Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 |
| abstract_unstemmed |
Abstract A simple ultra-low-voltage realization of second-generation voltage conveyor (VCII) based on the employment of super source follower, as voltage follower, and of current follower is presented in this paper. Full CMOS realization of the proposed VCII contains only ten transistors and two biasing voltages except for DC power supply voltages. Thanks to the super source follower structure, the parasitic resistance of the Z terminal is very low. As for parasitic resistance seen at the Y terminal, it can be reduced with the help of biasing voltage of current follower. Furthermore, its value can be tuned through the biasing voltage for different application circuits. Hence, this structure can be used as voltage-controlled second-generation voltage conveyor (VC-VCII). Post-layout simulation results, based on TSMC 0.18 μm CMOS process parameters, are provided. The main attractive features of the proposed VCII can be described as follows: operation under ± 0.45 V power supply voltages, consisting of only ten transistors, free from the body effect, capability of operating in a low-voltage environment, and parasitic resistance value at Z terminal equal to few Ohms. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021 |
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± 0.45 V CMOS Second-Generation Voltage Conveyor Based on Super Source Follower |
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https://dx.doi.org/10.1007/s00034-021-01867-7 |
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Minaei, Shahram Psychalinos, Costas |
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Minaei, Shahram Psychalinos, Costas |
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10.1007/s00034-021-01867-7 |
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2024-07-03T22:03:36.526Z |
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| score |
7.3999414 |