Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction

Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to th...
Ausführliche Beschreibung

Gespeichert in:
Autor*in:

Shinyamada, Kohei [verfasserIn]

Yamawaki, Akira

Format:

E-Artikel

Sprache:

Englisch

Erschienen:

2022

Schlagwörter:

FPGA

High-level synthesis

HLS

Image processing

Real camera system

Anmerkung:

© International Society of Artificial Life and Robotics (ISAROB) 2022

Übergeordnetes Werk:

Enthalten in: Artificial life and robotics - Berlin [u.a.] : Springer, 1997, 27(2022), 3 vom: 18. Juli, Seite 541-546

Übergeordnetes Werk:

volume:27 ; year:2022 ; number:3 ; day:18 ; month:07 ; pages:541-546

Links:

Volltext

DOI / URN:

10.1007/s10015-022-00777-4

Katalog-ID:

SPR047728191

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