Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction
Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to th...
Ausführliche Beschreibung
Autor*in: |
Shinyamada, Kohei [verfasserIn] |
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E-Artikel |
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Sprache: |
Englisch |
Erschienen: |
2022 |
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Anmerkung: |
© International Society of Artificial Life and Robotics (ISAROB) 2022 |
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Übergeordnetes Werk: |
Enthalten in: Artificial life and robotics - Berlin [u.a.] : Springer, 1997, 27(2022), 3 vom: 18. Juli, Seite 541-546 |
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Übergeordnetes Werk: |
volume:27 ; year:2022 ; number:3 ; day:18 ; month:07 ; pages:541-546 |
Links: |
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DOI / URN: |
10.1007/s10015-022-00777-4 |
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Katalog-ID: |
SPR047728191 |
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520 | |a Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. | ||
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10.1007/s10015-022-00777-4 doi (DE-627)SPR047728191 (SPR)s10015-022-00777-4-e DE-627 ger DE-627 rakwb eng Shinyamada, Kohei verfasserin aut Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © International Society of Artificial Life and Robotics (ISAROB) 2022 Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. FPGA (dpeaa)DE-He213 High-level synthesis (dpeaa)DE-He213 HLS (dpeaa)DE-He213 Image processing (dpeaa)DE-He213 Real camera system (dpeaa)DE-He213 Yamawaki, Akira aut Enthalten in Artificial life and robotics Berlin [u.a.] : Springer, 1997 27(2022), 3 vom: 18. Juli, Seite 541-546 (DE-627)271596678 (DE-600)1480655-1 1614-7456 nnns volume:27 year:2022 number:3 day:18 month:07 pages:541-546 https://dx.doi.org/10.1007/s10015-022-00777-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 27 2022 3 18 07 541-546 |
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10.1007/s10015-022-00777-4 doi (DE-627)SPR047728191 (SPR)s10015-022-00777-4-e DE-627 ger DE-627 rakwb eng Shinyamada, Kohei verfasserin aut Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © International Society of Artificial Life and Robotics (ISAROB) 2022 Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. FPGA (dpeaa)DE-He213 High-level synthesis (dpeaa)DE-He213 HLS (dpeaa)DE-He213 Image processing (dpeaa)DE-He213 Real camera system (dpeaa)DE-He213 Yamawaki, Akira aut Enthalten in Artificial life and robotics Berlin [u.a.] : Springer, 1997 27(2022), 3 vom: 18. Juli, Seite 541-546 (DE-627)271596678 (DE-600)1480655-1 1614-7456 nnns volume:27 year:2022 number:3 day:18 month:07 pages:541-546 https://dx.doi.org/10.1007/s10015-022-00777-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 27 2022 3 18 07 541-546 |
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10.1007/s10015-022-00777-4 doi (DE-627)SPR047728191 (SPR)s10015-022-00777-4-e DE-627 ger DE-627 rakwb eng Shinyamada, Kohei verfasserin aut Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © International Society of Artificial Life and Robotics (ISAROB) 2022 Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. FPGA (dpeaa)DE-He213 High-level synthesis (dpeaa)DE-He213 HLS (dpeaa)DE-He213 Image processing (dpeaa)DE-He213 Real camera system (dpeaa)DE-He213 Yamawaki, Akira aut Enthalten in Artificial life and robotics Berlin [u.a.] : Springer, 1997 27(2022), 3 vom: 18. Juli, Seite 541-546 (DE-627)271596678 (DE-600)1480655-1 1614-7456 nnns volume:27 year:2022 number:3 day:18 month:07 pages:541-546 https://dx.doi.org/10.1007/s10015-022-00777-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 27 2022 3 18 07 541-546 |
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10.1007/s10015-022-00777-4 doi (DE-627)SPR047728191 (SPR)s10015-022-00777-4-e DE-627 ger DE-627 rakwb eng Shinyamada, Kohei verfasserin aut Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © International Society of Artificial Life and Robotics (ISAROB) 2022 Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. FPGA (dpeaa)DE-He213 High-level synthesis (dpeaa)DE-He213 HLS (dpeaa)DE-He213 Image processing (dpeaa)DE-He213 Real camera system (dpeaa)DE-He213 Yamawaki, Akira aut Enthalten in Artificial life and robotics Berlin [u.a.] : Springer, 1997 27(2022), 3 vom: 18. Juli, Seite 541-546 (DE-627)271596678 (DE-600)1480655-1 1614-7456 nnns volume:27 year:2022 number:3 day:18 month:07 pages:541-546 https://dx.doi.org/10.1007/s10015-022-00777-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 27 2022 3 18 07 541-546 |
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Shinyamada, Kohei @@aut@@ Yamawaki, Akira @@aut@@ |
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Shinyamada, Kohei |
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Shinyamada, Kohei misc FPGA misc High-level synthesis misc HLS misc Image processing misc Real camera system Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction |
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Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction FPGA (dpeaa)DE-He213 High-level synthesis (dpeaa)DE-He213 HLS (dpeaa)DE-He213 Image processing (dpeaa)DE-He213 Real camera system (dpeaa)DE-He213 |
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Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction |
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Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction |
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Shinyamada, Kohei |
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development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction |
title_auth |
Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction |
abstract |
Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. © International Society of Artificial Life and Robotics (ISAROB) 2022 |
abstractGer |
Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. © International Society of Artificial Life and Robotics (ISAROB) 2022 |
abstract_unstemmed |
Abstract Hardware processing is more suitable for embedded image processing systems because of its higher performance and lower power consumption compared to software processing. In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing. © International Society of Artificial Life and Robotics (ISAROB) 2022 |
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Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction |
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https://dx.doi.org/10.1007/s10015-022-00777-4 |
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In order to gain market share in the rapidly expanding market, early development of products and early introduction to the market are essential. A high-level synthesis tool exists to support this. This tool automatically converts high-level languages into hardware description languages. In a real embedded system, maximum system performance and power saving can be achieved by an optimal combination of carefully generated high-level synthesis hardware and peripheral devices such as cameras and displays. We have developed a program description method for high-level synthesis of the median-based dynamic background subtraction method. In this study, the developed high-level synthesis hardware is installed in the system to obtain the maximum performance. The maximum frame rate, ignoring the performance of the real camera, was 166 fps when the image size was QVGA and the number of past time series data was %$N=4%$, which was very fast. Regardless of the image size, the hardware processing was more power efficient than the software processing.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">FPGA</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">High-level synthesis</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">HLS</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Image processing</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Real camera system</subfield><subfield code="7">(dpeaa)DE-He213</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Yamawaki, Akira</subfield><subfield code="4">aut</subfield></datafield><datafield tag="773" ind1="0" ind2="8"><subfield code="i">Enthalten in</subfield><subfield code="t">Artificial life and robotics</subfield><subfield code="d">Berlin [u.a.] : Springer, 1997</subfield><subfield code="g">27(2022), 3 vom: 18. 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