Bootstrapping techniques for energy-efficient successive approximation ADC
Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold ar...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Yuan, Fei [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2022 |
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| Schlagwörter: |
Successive approximation register analog-to-digital converters (SAR ADCs) |
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| Anmerkung: |
© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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| Übergeordnetes Werk: |
Enthalten in: Analog integrated circuits and signal processing - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991, 114(2022), 3 vom: 13. Okt., Seite 299-313 |
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| Übergeordnetes Werk: |
volume:114 ; year:2022 ; number:3 ; day:13 ; month:10 ; pages:299-313 |
| Links: |
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| DOI / URN: |
10.1007/s10470-022-02106-y |
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| Katalog-ID: |
SPR049995758 |
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| 520 | |a Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. | ||
| 650 | 4 | |a Successive approximation register analog-to-digital converters (SAR ADCs) |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Sample-and-hold (S/H) |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Bootstrapped switches |7 (dpeaa)DE-He213 | |
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10.1007/s10470-022-02106-y doi (DE-627)SPR049995758 (SPR)s10470-022-02106-y-e DE-627 ger DE-627 rakwb eng Yuan, Fei verfasserin aut Bootstrapping techniques for energy-efficient successive approximation ADC 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. Successive approximation register analog-to-digital converters (SAR ADCs) (dpeaa)DE-He213 Sample-and-hold (S/H) (dpeaa)DE-He213 Bootstrapped switches (dpeaa)DE-He213 Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 114(2022), 3 vom: 13. Okt., Seite 299-313 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:114 year:2022 number:3 day:13 month:10 pages:299-313 https://dx.doi.org/10.1007/s10470-022-02106-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 114 2022 3 13 10 299-313 |
| spelling |
10.1007/s10470-022-02106-y doi (DE-627)SPR049995758 (SPR)s10470-022-02106-y-e DE-627 ger DE-627 rakwb eng Yuan, Fei verfasserin aut Bootstrapping techniques for energy-efficient successive approximation ADC 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. Successive approximation register analog-to-digital converters (SAR ADCs) (dpeaa)DE-He213 Sample-and-hold (S/H) (dpeaa)DE-He213 Bootstrapped switches (dpeaa)DE-He213 Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 114(2022), 3 vom: 13. Okt., Seite 299-313 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:114 year:2022 number:3 day:13 month:10 pages:299-313 https://dx.doi.org/10.1007/s10470-022-02106-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 114 2022 3 13 10 299-313 |
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10.1007/s10470-022-02106-y doi (DE-627)SPR049995758 (SPR)s10470-022-02106-y-e DE-627 ger DE-627 rakwb eng Yuan, Fei verfasserin aut Bootstrapping techniques for energy-efficient successive approximation ADC 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. Successive approximation register analog-to-digital converters (SAR ADCs) (dpeaa)DE-He213 Sample-and-hold (S/H) (dpeaa)DE-He213 Bootstrapped switches (dpeaa)DE-He213 Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 114(2022), 3 vom: 13. Okt., Seite 299-313 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:114 year:2022 number:3 day:13 month:10 pages:299-313 https://dx.doi.org/10.1007/s10470-022-02106-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 114 2022 3 13 10 299-313 |
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10.1007/s10470-022-02106-y doi (DE-627)SPR049995758 (SPR)s10470-022-02106-y-e DE-627 ger DE-627 rakwb eng Yuan, Fei verfasserin aut Bootstrapping techniques for energy-efficient successive approximation ADC 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. Successive approximation register analog-to-digital converters (SAR ADCs) (dpeaa)DE-He213 Sample-and-hold (S/H) (dpeaa)DE-He213 Bootstrapped switches (dpeaa)DE-He213 Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 114(2022), 3 vom: 13. Okt., Seite 299-313 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:114 year:2022 number:3 day:13 month:10 pages:299-313 https://dx.doi.org/10.1007/s10470-022-02106-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 114 2022 3 13 10 299-313 |
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10.1007/s10470-022-02106-y doi (DE-627)SPR049995758 (SPR)s10470-022-02106-y-e DE-627 ger DE-627 rakwb eng Yuan, Fei verfasserin aut Bootstrapping techniques for energy-efficient successive approximation ADC 2022 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. Successive approximation register analog-to-digital converters (SAR ADCs) (dpeaa)DE-He213 Sample-and-hold (S/H) (dpeaa)DE-He213 Bootstrapped switches (dpeaa)DE-He213 Enthalten in Analog integrated circuits and signal processing Dordrecht [u.a.] : Springer Science + Business Media B.V, 1991 114(2022), 3 vom: 13. Okt., Seite 299-313 (DE-627)271348925 (DE-600)1479772-0 1573-1979 nnns volume:114 year:2022 number:3 day:13 month:10 pages:299-313 https://dx.doi.org/10.1007/s10470-022-02106-y lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 114 2022 3 13 10 299-313 |
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Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. 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Yuan, Fei |
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Yuan, Fei misc Successive approximation register analog-to-digital converters (SAR ADCs) misc Sample-and-hold (S/H) misc Bootstrapped switches Bootstrapping techniques for energy-efficient successive approximation ADC |
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Bootstrapping techniques for energy-efficient successive approximation ADC Successive approximation register analog-to-digital converters (SAR ADCs) (dpeaa)DE-He213 Sample-and-hold (S/H) (dpeaa)DE-He213 Bootstrapped switches (dpeaa)DE-He213 |
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bootstrapping techniques for energy-efficient successive approximation adc |
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Bootstrapping techniques for energy-efficient successive approximation ADC |
| abstract |
Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| abstractGer |
Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| abstract_unstemmed |
Abstract This paper provides a comparative study of bootstrapping techniques in energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping in sample-and-hold and the impact of bootstrapping voltage on the linearity of the sample-and hold are investigated. It is followed with an in-depth examination of the design, operations, advantages and disadvantages of reported bootstrapping techniques. Design considerations in choosing the value of the bootstrapping capacitor for minimizing the nonlinearity and resistance of the channel resistance of the sampling switch, that of the negative-gating capacitor for minimizing the leakage current of the sampling switch, and the dimension of the sampling switch to cope with the conversion rate of SAR ADC and proper bootstrapping voltage are investigated analytically. Detailed procedures to obtain the accurate spectrum of sample-and-holds are provided. The nonlinearity and power consumption of sample-and-holds with bootstrapped switches designed in a TSMC 130 nm 1.2 V CMOS technology are compared numerically. The impact of supply voltage reduction on the nonlinearity and power consumption of sample-and-holds with bootstrapped switches is also quantified using simulation results. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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Bootstrapping techniques for energy-efficient successive approximation ADC |
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