An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform
Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital im...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Harb, Salah [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2023 |
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| Schlagwörter: |
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| Anmerkung: |
© The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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| Übergeordnetes Werk: |
Enthalten in: Journal of real-time image processing - Berlin : Springer, 2006, 20(2023), 3 vom: 24. Apr. |
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| Übergeordnetes Werk: |
volume:20 ; year:2023 ; number:3 ; day:24 ; month:04 |
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| DOI / URN: |
10.1007/s11554-023-01302-x |
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| Katalog-ID: |
SPR050152211 |
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| 245 | 1 | 3 | |a An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform |
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| 520 | |a Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. | ||
| 650 | 4 | |a Image steganography |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Embedding |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a FPGA |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a ZYNQ |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a SoC |7 (dpeaa)DE-He213 | |
| 650 | 4 | |a Embedded system design |7 (dpeaa)DE-He213 | |
| 700 | 1 | |a Ahmad, M. Omair |4 aut | |
| 700 | 1 | |a Swamy, M. N. S. |4 aut | |
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10.1007/s11554-023-01302-x doi (DE-627)SPR050152211 (SPR)s11554-023-01302-x-e DE-627 ger DE-627 rakwb eng Harb, Salah verfasserin aut An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. Image steganography (dpeaa)DE-He213 Embedding (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 ZYNQ (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Embedded system design (dpeaa)DE-He213 Ahmad, M. Omair aut Swamy, M. N. S. aut Enthalten in Journal of real-time image processing Berlin : Springer, 2006 20(2023), 3 vom: 24. Apr. (DE-627)52836118X (DE-600)2280192-3 1861-8219 nnns volume:20 year:2023 number:3 day:24 month:04 https://dx.doi.org/10.1007/s11554-023-01302-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 20 2023 3 24 04 |
| spelling |
10.1007/s11554-023-01302-x doi (DE-627)SPR050152211 (SPR)s11554-023-01302-x-e DE-627 ger DE-627 rakwb eng Harb, Salah verfasserin aut An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. Image steganography (dpeaa)DE-He213 Embedding (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 ZYNQ (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Embedded system design (dpeaa)DE-He213 Ahmad, M. Omair aut Swamy, M. N. S. aut Enthalten in Journal of real-time image processing Berlin : Springer, 2006 20(2023), 3 vom: 24. Apr. (DE-627)52836118X (DE-600)2280192-3 1861-8219 nnns volume:20 year:2023 number:3 day:24 month:04 https://dx.doi.org/10.1007/s11554-023-01302-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 20 2023 3 24 04 |
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10.1007/s11554-023-01302-x doi (DE-627)SPR050152211 (SPR)s11554-023-01302-x-e DE-627 ger DE-627 rakwb eng Harb, Salah verfasserin aut An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. Image steganography (dpeaa)DE-He213 Embedding (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 ZYNQ (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Embedded system design (dpeaa)DE-He213 Ahmad, M. Omair aut Swamy, M. N. S. aut Enthalten in Journal of real-time image processing Berlin : Springer, 2006 20(2023), 3 vom: 24. Apr. (DE-627)52836118X (DE-600)2280192-3 1861-8219 nnns volume:20 year:2023 number:3 day:24 month:04 https://dx.doi.org/10.1007/s11554-023-01302-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 20 2023 3 24 04 |
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10.1007/s11554-023-01302-x doi (DE-627)SPR050152211 (SPR)s11554-023-01302-x-e DE-627 ger DE-627 rakwb eng Harb, Salah verfasserin aut An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. Image steganography (dpeaa)DE-He213 Embedding (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 ZYNQ (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Embedded system design (dpeaa)DE-He213 Ahmad, M. Omair aut Swamy, M. N. S. aut Enthalten in Journal of real-time image processing Berlin : Springer, 2006 20(2023), 3 vom: 24. Apr. (DE-627)52836118X (DE-600)2280192-3 1861-8219 nnns volume:20 year:2023 number:3 day:24 month:04 https://dx.doi.org/10.1007/s11554-023-01302-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 20 2023 3 24 04 |
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10.1007/s11554-023-01302-x doi (DE-627)SPR050152211 (SPR)s11554-023-01302-x-e DE-627 ger DE-627 rakwb eng Harb, Salah verfasserin aut An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. Image steganography (dpeaa)DE-He213 Embedding (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 ZYNQ (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Embedded system design (dpeaa)DE-He213 Ahmad, M. Omair aut Swamy, M. N. S. aut Enthalten in Journal of real-time image processing Berlin : Springer, 2006 20(2023), 3 vom: 24. Apr. (DE-627)52836118X (DE-600)2280192-3 1861-8219 nnns volume:20 year:2023 number:3 day:24 month:04 https://dx.doi.org/10.1007/s11554-023-01302-x lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 20 2023 3 24 04 |
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Harb, Salah |
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Harb, Salah misc Image steganography misc Embedding misc FPGA misc ZYNQ misc SoC misc Embedded system design An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform |
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An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform Image steganography (dpeaa)DE-He213 Embedding (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 ZYNQ (dpeaa)DE-He213 SoC (dpeaa)DE-He213 Embedded system design (dpeaa)DE-He213 |
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efficient image steganographic scheme for a real-time embedded system and its hardware implementation on amd xilinx zynq-7000 apsoc platform |
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An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform |
| abstract |
Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| abstractGer |
Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| abstract_unstemmed |
Abstract As a pivotal advance in the field of information security, steganography holds a crucial place in concealing sensitive information. It is the technique of hiding secret data within a digital media carrier, such as an image. An image steganographic scheme conceals secret data in a digital image by manipulating pixel values in a way that the data is undetectable to unauthorized parties in communication channels. These schemes are widely used for various real-time applications, including but not limited to content authentication, copyright protection, and biometric data protection. To effectively process image steganographic schemes in real-time applications, it is important to reduce computational delay and increase throughput. Implementing these schemes on a reconfigurable hardware platform is an efficient way to achieve these tasks. In this paper, we present a reconfigurable embedded system for an efficient steganographic scheme that embeds and recovers secret data in digital images using the AMD Xilinx Zynq-7000 all programmable system-on-chip (APSoC) platform. The system demonstrates real-time processing capabilities, delivering a frame rate of 30.7 FPS for a full high-definition RGB image, surpassing recent hardware implementations in terms of speed, resource utilization, and system throughput. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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An efficient image steganographic scheme for a real-time embedded system and its hardware implementation on AMD Xilinx Zynq-7000 APSoC platform |
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Ahmad, M. Omair Swamy, M. N. S. |
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|
| score |
7.399987 |