A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application
Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To over...
Ausführliche Beschreibung
Gespeichert in:
| Autor*in: |
Xu, Bo [verfasserIn] |
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| Format: |
E-Artikel |
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| Sprache: |
Englisch |
| Erschienen: |
2023 |
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| Schlagwörter: |
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| Anmerkung: |
© The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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| Übergeordnetes Werk: |
Enthalten in: Nonlinear dynamics - Dordrecht [u.a.] : Springer Science + Business Media B.V, 1990, 112(2023), 2 vom: 15. Dez., Seite 1395-1414 |
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| Übergeordnetes Werk: |
volume:112 ; year:2023 ; number:2 ; day:15 ; month:12 ; pages:1395-1414 |
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| DOI / URN: |
10.1007/s11071-023-09092-4 |
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| Katalog-ID: |
SPR054153204 |
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| 520 | |a Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. | ||
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| 700 | 1 | |a Zhao, Jia |0 (orcid)0009-0006-5849-4324 |4 aut | |
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10.1007/s11071-023-09092-4 doi (DE-627)SPR054153204 (SPR)s11071-023-09092-4-e DE-627 ger DE-627 rakwb eng Xu, Bo verfasserin (orcid)0000-0002-0765-0976 aut A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. Memristor mathematical model (dpeaa)DE-He213 Maximum operating frequency (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 General memristor simulator (dpeaa)DE-He213 Chaotic oscillator (dpeaa)DE-He213 Zou, Songting aut Bai, Libing (orcid)0000-0001-8906-0576 aut Chen, Kai (orcid)0000-0001-9520-4273 aut Zhao, Jia (orcid)0009-0006-5849-4324 aut Enthalten in Nonlinear dynamics Dordrecht [u.a.] : Springer Science + Business Media B.V, 1990 112(2023), 2 vom: 15. Dez., Seite 1395-1414 (DE-627)315297034 (DE-600)2012600-1 1573-269X nnns volume:112 year:2023 number:2 day:15 month:12 pages:1395-1414 https://dx.doi.org/10.1007/s11071-023-09092-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 112 2023 2 15 12 1395-1414 |
| spelling |
10.1007/s11071-023-09092-4 doi (DE-627)SPR054153204 (SPR)s11071-023-09092-4-e DE-627 ger DE-627 rakwb eng Xu, Bo verfasserin (orcid)0000-0002-0765-0976 aut A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. Memristor mathematical model (dpeaa)DE-He213 Maximum operating frequency (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 General memristor simulator (dpeaa)DE-He213 Chaotic oscillator (dpeaa)DE-He213 Zou, Songting aut Bai, Libing (orcid)0000-0001-8906-0576 aut Chen, Kai (orcid)0000-0001-9520-4273 aut Zhao, Jia (orcid)0009-0006-5849-4324 aut Enthalten in Nonlinear dynamics Dordrecht [u.a.] : Springer Science + Business Media B.V, 1990 112(2023), 2 vom: 15. Dez., Seite 1395-1414 (DE-627)315297034 (DE-600)2012600-1 1573-269X nnns volume:112 year:2023 number:2 day:15 month:12 pages:1395-1414 https://dx.doi.org/10.1007/s11071-023-09092-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 112 2023 2 15 12 1395-1414 |
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10.1007/s11071-023-09092-4 doi (DE-627)SPR054153204 (SPR)s11071-023-09092-4-e DE-627 ger DE-627 rakwb eng Xu, Bo verfasserin (orcid)0000-0002-0765-0976 aut A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. Memristor mathematical model (dpeaa)DE-He213 Maximum operating frequency (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 General memristor simulator (dpeaa)DE-He213 Chaotic oscillator (dpeaa)DE-He213 Zou, Songting aut Bai, Libing (orcid)0000-0001-8906-0576 aut Chen, Kai (orcid)0000-0001-9520-4273 aut Zhao, Jia (orcid)0009-0006-5849-4324 aut Enthalten in Nonlinear dynamics Dordrecht [u.a.] : Springer Science + Business Media B.V, 1990 112(2023), 2 vom: 15. Dez., Seite 1395-1414 (DE-627)315297034 (DE-600)2012600-1 1573-269X nnns volume:112 year:2023 number:2 day:15 month:12 pages:1395-1414 https://dx.doi.org/10.1007/s11071-023-09092-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 112 2023 2 15 12 1395-1414 |
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10.1007/s11071-023-09092-4 doi (DE-627)SPR054153204 (SPR)s11071-023-09092-4-e DE-627 ger DE-627 rakwb eng Xu, Bo verfasserin (orcid)0000-0002-0765-0976 aut A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. Memristor mathematical model (dpeaa)DE-He213 Maximum operating frequency (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 General memristor simulator (dpeaa)DE-He213 Chaotic oscillator (dpeaa)DE-He213 Zou, Songting aut Bai, Libing (orcid)0000-0001-8906-0576 aut Chen, Kai (orcid)0000-0001-9520-4273 aut Zhao, Jia (orcid)0009-0006-5849-4324 aut Enthalten in Nonlinear dynamics Dordrecht [u.a.] : Springer Science + Business Media B.V, 1990 112(2023), 2 vom: 15. Dez., Seite 1395-1414 (DE-627)315297034 (DE-600)2012600-1 1573-269X nnns volume:112 year:2023 number:2 day:15 month:12 pages:1395-1414 https://dx.doi.org/10.1007/s11071-023-09092-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 112 2023 2 15 12 1395-1414 |
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10.1007/s11071-023-09092-4 doi (DE-627)SPR054153204 (SPR)s11071-023-09092-4-e DE-627 ger DE-627 rakwb eng Xu, Bo verfasserin (orcid)0000-0002-0765-0976 aut A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application 2023 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. Memristor mathematical model (dpeaa)DE-He213 Maximum operating frequency (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 General memristor simulator (dpeaa)DE-He213 Chaotic oscillator (dpeaa)DE-He213 Zou, Songting aut Bai, Libing (orcid)0000-0001-8906-0576 aut Chen, Kai (orcid)0000-0001-9520-4273 aut Zhao, Jia (orcid)0009-0006-5849-4324 aut Enthalten in Nonlinear dynamics Dordrecht [u.a.] : Springer Science + Business Media B.V, 1990 112(2023), 2 vom: 15. Dez., Seite 1395-1414 (DE-627)315297034 (DE-600)2012600-1 1573-269X nnns volume:112 year:2023 number:2 day:15 month:12 pages:1395-1414 https://dx.doi.org/10.1007/s11071-023-09092-4 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER GBV_ILN_11 GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_63 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_150 GBV_ILN_151 GBV_ILN_152 GBV_ILN_161 GBV_ILN_170 GBV_ILN_171 GBV_ILN_187 GBV_ILN_213 GBV_ILN_224 GBV_ILN_230 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_636 GBV_ILN_702 GBV_ILN_2001 GBV_ILN_2003 GBV_ILN_2004 GBV_ILN_2005 GBV_ILN_2006 GBV_ILN_2007 GBV_ILN_2008 GBV_ILN_2009 GBV_ILN_2010 GBV_ILN_2011 GBV_ILN_2014 GBV_ILN_2015 GBV_ILN_2020 GBV_ILN_2021 GBV_ILN_2025 GBV_ILN_2026 GBV_ILN_2027 GBV_ILN_2031 GBV_ILN_2034 GBV_ILN_2037 GBV_ILN_2038 GBV_ILN_2039 GBV_ILN_2044 GBV_ILN_2048 GBV_ILN_2049 GBV_ILN_2050 GBV_ILN_2055 GBV_ILN_2056 GBV_ILN_2057 GBV_ILN_2059 GBV_ILN_2061 GBV_ILN_2064 GBV_ILN_2065 GBV_ILN_2068 GBV_ILN_2088 GBV_ILN_2093 GBV_ILN_2106 GBV_ILN_2107 GBV_ILN_2108 GBV_ILN_2110 GBV_ILN_2111 GBV_ILN_2112 GBV_ILN_2113 GBV_ILN_2118 GBV_ILN_2122 GBV_ILN_2129 GBV_ILN_2143 GBV_ILN_2144 GBV_ILN_2147 GBV_ILN_2148 GBV_ILN_2152 GBV_ILN_2153 GBV_ILN_2188 GBV_ILN_2190 GBV_ILN_2232 GBV_ILN_2336 GBV_ILN_2446 GBV_ILN_2470 GBV_ILN_2472 GBV_ILN_2507 GBV_ILN_2522 GBV_ILN_2548 GBV_ILN_4035 GBV_ILN_4037 GBV_ILN_4046 GBV_ILN_4112 GBV_ILN_4125 GBV_ILN_4126 GBV_ILN_4242 GBV_ILN_4246 GBV_ILN_4249 GBV_ILN_4251 GBV_ILN_4305 GBV_ILN_4306 GBV_ILN_4307 GBV_ILN_4313 GBV_ILN_4322 GBV_ILN_4323 GBV_ILN_4324 GBV_ILN_4325 GBV_ILN_4326 GBV_ILN_4328 GBV_ILN_4333 GBV_ILN_4334 GBV_ILN_4335 GBV_ILN_4336 GBV_ILN_4338 GBV_ILN_4393 GBV_ILN_4700 AR 112 2023 2 15 12 1395-1414 |
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<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01000naa a22002652 4500</leader><controlfield tag="001">SPR054153204</controlfield><controlfield tag="003">DE-627</controlfield><controlfield tag="005">20231222064648.0</controlfield><controlfield tag="007">cr uuu---uuuuu</controlfield><controlfield tag="008">231222s2023 xx |||||o 00| ||eng c</controlfield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/s11071-023-09092-4</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-627)SPR054153204</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(SPR)s11071-023-09092-4-e</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-627</subfield><subfield code="b">ger</subfield><subfield code="c">DE-627</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Xu, Bo</subfield><subfield code="e">verfasserin</subfield><subfield code="0">(orcid)0000-0002-0765-0976</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="2"><subfield code="a">A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="c">2023</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="a">Text</subfield><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="a">Computermedien</subfield><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="a">Online-Ressource</subfield><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">© The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. 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Xu, Bo |
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A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application Memristor mathematical model (dpeaa)DE-He213 Maximum operating frequency (dpeaa)DE-He213 FPGA (dpeaa)DE-He213 General memristor simulator (dpeaa)DE-He213 Chaotic oscillator (dpeaa)DE-He213 |
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general discrete memristor emulator based on taylor expansion for the reconfigurable fpga implementation and its application |
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A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application |
| abstract |
Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| abstractGer |
Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
| abstract_unstemmed |
Abstract The research on the memristor model and its high-precision hardware circuit experimental platform has gained significant attention. This paper presents a general discrete memristor emulator (GDME) and investigates its typical dynamic properties and operating frequency theoretically. To overcome the limitations of noise and bandwidth of commercial components on pinched hysteresis loops (PHLs), an operating frequency shifting method is proposed. An FPGA-based GDME hardware experiment platform is integrated into an acquisition card, enabling the digital domain processing of signals at the memristor’s two ports and showing the PHLs. The proposed method achieves an experimental maximum operating frequency (EMOF) of 20 GHz, approximately 3.3e3 times better than the existing method. Subsequently, the EMOF and PHLs of existing memristor models are expanded using a tenth-order GDME. Experimental results demonstrate that the proposed method exhibits high accuracy, reconfigurability, and speed. Finally, a 2D memristor logistic map of a coupled third-order GDME is designed, and the performance analysis reveals that the coupled memristor can further improve its stochastic performance. © The Author(s), under exclusive licence to Springer Nature B.V. 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law. |
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A general discrete memristor emulator based on Taylor expansion for the reconfigurable FPGA implementation and its application |
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https://dx.doi.org/10.1007/s11071-023-09092-4 |
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Zou, Songting Bai, Libing Chen, Kai Zhao, Jia |
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10.1007/s11071-023-09092-4 |
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| score |
7.3988657 |