A low power and small area all digital delay-locked loop based on ring oscillator architecture

Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain...
Ausführliche Beschreibung

Gespeichert in:

Autor*in:	Zheng, JiaPeng [verfasserIn] Li, Wei [verfasserIn] Lu, XueQing [verfasserIn] Cheng, YuHua [verfasserIn] Wang, YangYuan [verfasserIn]

Format:	E-Artikel
Sprache:	Englisch

Erschienen:	2011

Schlagwörter:	all digital delay locked loop (DLL) phase locked loop (PLL) ring oscillator

Übergeordnetes Werk:	Enthalten in: Science in China - Heidelberg : Springer, 2001, 55(2011), 2 vom: 10. Juni, Seite 453-460
Übergeordnetes Werk:	volume:55 ; year:2011 ; number:2 ; day:10 ; month:06 ; pages:453-460

Links:	Volltext

DOI / URN:	10.1007/s11432-011-4278-8

Katalog-ID:	SPR019307748

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520			\|a Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.
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allfields	10.1007/s11432-011-4278-8 doi (DE-627)SPR019307748 (SPR)s11432-011-4278-8-e DE-627 ger DE-627 rakwb eng 070 004 ASE 54.00 bkl Zheng, JiaPeng verfasserin aut A low power and small area all digital delay-locked loop based on ring oscillator architecture 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. all digital (dpeaa)DE-He213 delay locked loop (DLL) (dpeaa)DE-He213 phase locked loop (PLL) (dpeaa)DE-He213 ring oscillator (dpeaa)DE-He213 Li, Wei verfasserin aut Lu, XueQing verfasserin aut Cheng, YuHua verfasserin aut Wang, YangYuan verfasserin aut Enthalten in Science in China Heidelberg : Springer, 2001 55(2011), 2 vom: 10. Juni, Seite 453-460 (DE-627)385614764 (DE-600)2142898-0 1862-2836 nnns volume:55 year:2011 number:2 day:10 month:06 pages:453-460 https://dx.doi.org/10.1007/s11432-011-4278-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-BBI SSG-OPC-ASE GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_152 GBV_ILN_161 GBV_ILN_171 GBV_ILN_187 GBV_ILN_224 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 54.00 ASE AR 55 2011 2 10 06 453-460
spelling	10.1007/s11432-011-4278-8 doi (DE-627)SPR019307748 (SPR)s11432-011-4278-8-e DE-627 ger DE-627 rakwb eng 070 004 ASE 54.00 bkl Zheng, JiaPeng verfasserin aut A low power and small area all digital delay-locked loop based on ring oscillator architecture 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. all digital (dpeaa)DE-He213 delay locked loop (DLL) (dpeaa)DE-He213 phase locked loop (PLL) (dpeaa)DE-He213 ring oscillator (dpeaa)DE-He213 Li, Wei verfasserin aut Lu, XueQing verfasserin aut Cheng, YuHua verfasserin aut Wang, YangYuan verfasserin aut Enthalten in Science in China Heidelberg : Springer, 2001 55(2011), 2 vom: 10. Juni, Seite 453-460 (DE-627)385614764 (DE-600)2142898-0 1862-2836 nnns volume:55 year:2011 number:2 day:10 month:06 pages:453-460 https://dx.doi.org/10.1007/s11432-011-4278-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-BBI SSG-OPC-ASE GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_152 GBV_ILN_161 GBV_ILN_171 GBV_ILN_187 GBV_ILN_224 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 54.00 ASE AR 55 2011 2 10 06 453-460
allfields_unstemmed	10.1007/s11432-011-4278-8 doi (DE-627)SPR019307748 (SPR)s11432-011-4278-8-e DE-627 ger DE-627 rakwb eng 070 004 ASE 54.00 bkl Zheng, JiaPeng verfasserin aut A low power and small area all digital delay-locked loop based on ring oscillator architecture 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. all digital (dpeaa)DE-He213 delay locked loop (DLL) (dpeaa)DE-He213 phase locked loop (PLL) (dpeaa)DE-He213 ring oscillator (dpeaa)DE-He213 Li, Wei verfasserin aut Lu, XueQing verfasserin aut Cheng, YuHua verfasserin aut Wang, YangYuan verfasserin aut Enthalten in Science in China Heidelberg : Springer, 2001 55(2011), 2 vom: 10. Juni, Seite 453-460 (DE-627)385614764 (DE-600)2142898-0 1862-2836 nnns volume:55 year:2011 number:2 day:10 month:06 pages:453-460 https://dx.doi.org/10.1007/s11432-011-4278-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-BBI SSG-OPC-ASE GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_152 GBV_ILN_161 GBV_ILN_171 GBV_ILN_187 GBV_ILN_224 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 54.00 ASE AR 55 2011 2 10 06 453-460
allfieldsGer	10.1007/s11432-011-4278-8 doi (DE-627)SPR019307748 (SPR)s11432-011-4278-8-e DE-627 ger DE-627 rakwb eng 070 004 ASE 54.00 bkl Zheng, JiaPeng verfasserin aut A low power and small area all digital delay-locked loop based on ring oscillator architecture 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. all digital (dpeaa)DE-He213 delay locked loop (DLL) (dpeaa)DE-He213 phase locked loop (PLL) (dpeaa)DE-He213 ring oscillator (dpeaa)DE-He213 Li, Wei verfasserin aut Lu, XueQing verfasserin aut Cheng, YuHua verfasserin aut Wang, YangYuan verfasserin aut Enthalten in Science in China Heidelberg : Springer, 2001 55(2011), 2 vom: 10. Juni, Seite 453-460 (DE-627)385614764 (DE-600)2142898-0 1862-2836 nnns volume:55 year:2011 number:2 day:10 month:06 pages:453-460 https://dx.doi.org/10.1007/s11432-011-4278-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-BBI SSG-OPC-ASE GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_152 GBV_ILN_161 GBV_ILN_171 GBV_ILN_187 GBV_ILN_224 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 54.00 ASE AR 55 2011 2 10 06 453-460
allfieldsSound	10.1007/s11432-011-4278-8 doi (DE-627)SPR019307748 (SPR)s11432-011-4278-8-e DE-627 ger DE-627 rakwb eng 070 004 ASE 54.00 bkl Zheng, JiaPeng verfasserin aut A low power and small area all digital delay-locked loop based on ring oscillator architecture 2011 Text txt rdacontent Computermedien c rdamedia Online-Ressource cr rdacarrier Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. all digital (dpeaa)DE-He213 delay locked loop (DLL) (dpeaa)DE-He213 phase locked loop (PLL) (dpeaa)DE-He213 ring oscillator (dpeaa)DE-He213 Li, Wei verfasserin aut Lu, XueQing verfasserin aut Cheng, YuHua verfasserin aut Wang, YangYuan verfasserin aut Enthalten in Science in China Heidelberg : Springer, 2001 55(2011), 2 vom: 10. Juni, Seite 453-460 (DE-627)385614764 (DE-600)2142898-0 1862-2836 nnns volume:55 year:2011 number:2 day:10 month:06 pages:453-460 https://dx.doi.org/10.1007/s11432-011-4278-8 lizenzpflichtig Volltext GBV_USEFLAG_A SYSFLAG_A GBV_SPRINGER SSG-OPC-BBI SSG-OPC-ASE GBV_ILN_20 GBV_ILN_22 GBV_ILN_23 GBV_ILN_24 GBV_ILN_31 GBV_ILN_32 GBV_ILN_39 GBV_ILN_40 GBV_ILN_60 GBV_ILN_62 GBV_ILN_65 GBV_ILN_69 GBV_ILN_70 GBV_ILN_73 GBV_ILN_74 GBV_ILN_90 GBV_ILN_95 GBV_ILN_100 GBV_ILN_101 GBV_ILN_105 GBV_ILN_110 GBV_ILN_120 GBV_ILN_138 GBV_ILN_152 GBV_ILN_161 GBV_ILN_171 GBV_ILN_187 GBV_ILN_224 GBV_ILN_250 GBV_ILN_281 GBV_ILN_285 GBV_ILN_293 GBV_ILN_370 GBV_ILN_602 GBV_ILN_702 54.00 ASE AR 55 2011 2 10 06 453-460
language	English
source	Enthalten in Science in China 55(2011), 2 vom: 10. Juni, Seite 453-460 volume:55 year:2011 number:2 day:10 month:06 pages:453-460
sourceStr	Enthalten in Science in China 55(2011), 2 vom: 10. Juni, Seite 453-460 volume:55 year:2011 number:2 day:10 month:06 pages:453-460
format_phy_str_mv	Article
institution	findex.gbv.de
topic_facet	all digital delay locked loop (DLL) phase locked loop (PLL) ring oscillator
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container_title	Science in China
authorswithroles_txt_mv	Zheng, JiaPeng @@aut@@ Li, Wei @@aut@@ Lu, XueQing @@aut@@ Cheng, YuHua @@aut@@ Wang, YangYuan @@aut@@
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author	Zheng, JiaPeng
spellingShingle	Zheng, JiaPeng ddc 070 bkl 54.00 misc all digital misc delay locked loop (DLL) misc phase locked loop (PLL) misc ring oscillator A low power and small area all digital delay-locked loop based on ring oscillator architecture
authorStr	Zheng, JiaPeng
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topic_title	070 004 ASE 54.00 bkl A low power and small area all digital delay-locked loop based on ring oscillator architecture all digital (dpeaa)DE-He213 delay locked loop (DLL) (dpeaa)DE-He213 phase locked loop (PLL) (dpeaa)DE-He213 ring oscillator (dpeaa)DE-He213
topic	ddc 070 bkl 54.00 misc all digital misc delay locked loop (DLL) misc phase locked loop (PLL) misc ring oscillator
topic_unstemmed	ddc 070 bkl 54.00 misc all digital misc delay locked loop (DLL) misc phase locked loop (PLL) misc ring oscillator
topic_browse	ddc 070 bkl 54.00 misc all digital misc delay locked loop (DLL) misc phase locked loop (PLL) misc ring oscillator
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title	A low power and small area all digital delay-locked loop based on ring oscillator architecture
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title_full	A low power and small area all digital delay-locked loop based on ring oscillator architecture
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author_browse	Zheng, JiaPeng Li, Wei Lu, XueQing Cheng, YuHua Wang, YangYuan
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doi_str_mv	10.1007/s11432-011-4278-8
dewey-full	070 004
author2-role	verfasserin
title_sort	low power and small area all digital delay-locked loop based on ring oscillator architecture
title_auth	A low power and small area all digital delay-locked loop based on ring oscillator architecture
abstract	Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.
abstractGer	Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.
abstract_unstemmed	Abstract A 133–500 MHz, 5.2 mW500 MHz, 0.021 $ mm^{2} $ all digital delay-locked loop (ADDLL) is presented. The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator (ROSC) to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed. The proposed ADDLL has better immunity to PVT (process, voltage, and temperature) than most conventional DLLs, which do not update the control word signals after the locking process, since the control signals for slave delay line are updated in every 256 reference cycles. Fabricated in 0.13 um CMOS process, the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.
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title_short	A low power and small area all digital delay-locked loop based on ring oscillator architecture
url	https://dx.doi.org/10.1007/s11432-011-4278-8
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author2	Li, Wei Lu, XueQing Cheng, YuHua Wang, YangYuan
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up_date	2024-07-04T01:03:04.657Z
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